Jump to main content
Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security
Search
Product Pages
SAMA7G54
Home
2
CPU and Interconnect
2.9
Boot Strategies
2.9.3
Key Provisioning and Bootstrap Programming
2.9.3.2
Bootstrap Development and Updates
2.9.3.2.2
Bootstrap Field Update
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
2.1
Event System
2.2
System Interconnect and Security (SIS)
2.3
Cortex-A7 Processor (Arm)
2.4
External Interrupt Controller (EIC)
2.5
Debug and Test
2.6
NIC-400 Global Programmer’s View (NICGPV)
2.7
Bus Matrix (MATRIX)
2.8
DMA Controller (XDMAC)
2.9
Boot Strategies
2.9.1
Standard Boot Strategy
2.9.2
Secure Boot Strategy
2.9.3
Key Provisioning and Bootstrap Programming
2.9.3.1
Configuring Secure Boot Mode
2.9.3.2
Bootstrap Development and Updates
2.9.3.2.1
Bootstrap Ciphering
2.9.3.2.2
Bootstrap Field Update
2.9.3.2.2.1
Case 1: SAM-BA Monitor is disabled (the “MON_DIS” word is filled in the Boot Configuration Packet)
2.9.3.2.2.2
Case 2: Secure SAM-BA Monitor is still available (the “MON_DIS” word is zeroed in the Boot Configuration Packet - not recommended for systems in production)
2.9.3.3
Monitor Disabling by the Bootstrap
3
Memories
4
System Controller
5
Analog Subsystem
6
Image Subsystem
7
Audio Subsystem
8
Security and Cryptography Subsystem
9
Connectivity Subsystem
10
USB Subsystem
11
Electrical and Mechanical Characteristics
12
Glossary
13
Revision History
Microchip Information
2.9.3.2.2 Bootstrap Field Update
