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Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security
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SAMA7G54
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9
Connectivity Subsystem
9.2
Gigabit
Ethernet MAC (GMAC)
9.2.6
Functional Description
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Analog Subsystem
6
Image Subsystem
7
Audio Subsystem
8
Security and Cryptography Subsystem
9
Connectivity Subsystem
9.1
Overview
9.2
Gigabit
Ethernet MAC (GMAC)
9.2.1
Description
9.2.2
Embedded Characteristics
9.2.3
Block Diagram
9.2.4
Signal Interfaces
9.2.5
Product Dependencies
9.2.6
Functional Description
9.2.6.1
Media Access Controller
9.2.6.2
1588 Timestamp Unit
9.2.6.3
Direct Memory Access Interface
9.2.6.4
MAC Transmit Block
9.2.6.5
Transmit Scheduling Algorithm
9.2.6.6
MAC Receive Block
9.2.6.7
Checksum Offload for IP, TCP and UDP
9.2.6.8
MAC Filtering Block
9.2.6.9
Broadcast Address
9.2.6.10
Hash Addressing
9.2.6.11
Copy all Frames (Promiscuous Mode)
9.2.6.12
Disable Copy of Pause Frames
9.2.6.13
VLAN Support
9.2.6.14
Wake on LAN Support
9.2.6.15
IEEE 1588 Support
9.2.6.16
MAC 802.3 Pause Frame Support
9.2.6.17
MAC PFC Priority-based Pause Frame Support
9.2.6.18
Energy-efficient Ethernet Support
9.2.6.19
LPI Operation in the GMAC
9.2.6.20
PHY Interface
9.2.6.21
10/100
/1000
Operation
9.2.6.22
Jumbo Frames
9.2.7
Programming Interface
9.2
Register Summary
9.3
Flexible Serial Communication Controller (FLEXCOM)
9.4
Quad Serial Peripheral Interface (QSPI)
9.5
Secure Digital MultiMedia Card Controller (SDMMC)
9.6
Controller Area Network (MCAN)
9.7
Timer Counter (TC)
9.8
Pulse Width Modulation Controller (PWM)
10
USB Subsystem
11
Electrical and Mechanical Characteristics
12
Glossary
13
Revision History
Microchip Information
9.2.6 Functional Description
