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Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security
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SAMA7G54
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7
Audio Subsystem
7.3
Synchronous Serial Controller (SSC)
7.3.8
Functional Description
7.3.8.6
Receive Compare Modes
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Analog Subsystem
6
Image Subsystem
7
Audio Subsystem
7.1
Overview
7.2
Inter-IC Sound Multi-Channel Controller (I2SMCC)
7.3
Synchronous Serial Controller (SSC)
7.3.1
Description
7.3.2
Embedded Characteristics
7.3.3
Block Diagram
7.3.4
Application Block Diagram
7.3.5
SSC Application Examples
7.3.6
Pin Name List
7.3.7
Product Dependencies
7.3.8
Functional Description
7.3.8.1
Clock Management
7.3.8.2
Transmit Operations
7.3.8.3
Receive Operations
7.3.8.4
Start
7.3.8.5
Frame Synchronization
7.3.8.6
Receive Compare Modes
7.3.8.6.1
Compare Functions
7.3.8.7
Data Format
7.3.8.8
Loop Mode
7.3.8.9
Interrupt
7.3.8.10
Register Write Protection
7.3.9
Register Summary
7.4
Sony/Philips Digital Interface Receiver (SPDIFRX)
7.5
Sony/Philips Digital Interface Transmitter (SPDIFTX)
7.6
Pulse Density Microphone Controller (PDMC)
7.7
Asynchronous Sample Rate Converter (ASRC)
8
Security and Cryptography Subsystem
9
Connectivity Subsystem
10
USB Subsystem
11
Electrical and Mechanical Characteristics
12
Glossary
13
Revision History
Microchip Information
7.3.8.6 Receive Compare Modes
Figure 7-25.
Receive Compare Modes
