2.8.4 DMA Controller Peripheral Connections

DMA hardware requests are the same for XDMAC0 and XDMAC1. XDMAC2 is memory-to-memory dedicated, there is no hardware interface.

Table 2-17. DMA Channels Definitions (XDMAC0 and XDMAC1)
Instance NameChannel Transmit/ReceiveDMA Channel Hardware Interface NumberComments
ADCReceive0
AESTransmit1
AESReceive2
FLEXCOM0Receive5
FLEXCOM0Transmit6
FLEXCOM1Receive7
FLEXCOM1Transmit8
FLEXCOM2Receive9
FLEXCOM2Transmit10
FLEXCOM3Receive11
FLEXCOM3Transmit12
FLEXCOM4Receive13
FLEXCOM4Transmit14
FLEXCOM5Receive15
FLEXCOM5Transmit16
FLEXCOM6Receive17
FLEXCOM6Transmit18
FLEXCOM7Receive19
FLEXCOM7Transmit20
FLEXCOM8Receive21
FLEXCOM8Transmit22
FLEXCOM9Receive23
FLEXCOM9Transmit24
FLEXCOM10Receive25
FLEXCOM10Transmit26
FLEXCOM11Receive27
FLEXCOM11Transmit28
I2SMCC0Receive33
I2SMCC0Transmit34
I2SMCC1Receive35
I2SMCC1Transmit36
PDMC0Receive37
PDMC1Receive38
PWMTransmit39
QSPI0Receive40
QSPI0Transmit41
QSPI1Receive42
QSPI1Transmit43
SSC0Receive44
SSC0Transmit45
SSC1Receive46
SSC1Transmit47
SHATransmit48
SPDIFRXReceive49
SPDIFTXTransmit50
TC0Receive51
TC1Receive52
TDESReceive53
TDESTransmit54
ASRCR055
ASRCT056
ASRCR157
ASRCT158
ASRCR259
ASRCT260
ASRCR361
ASRCT362
TC0_CHANNEL1CPA63
TC1_CHANNEL1CPA64
TC0_CHANNEL1CPB65
TC1_CHANNEL1CPB66
TC0_CHANNEL1CPC67
TC1_CHANNEL1CPC68
TC0_CHANNEL1ETRG69
TC1_CHANNEL1ETRG70
Reserved71-126Do not use
Reserved127Memory-to-memory transfer