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2 CPU and Interconnect
2.9 Boot Strategies
2.9.1 Standard Boot Strategy
2.9.1.4 Standard Boot Configuration
2.9.1.4.13 Detailed Memory Boot Procedures

Introduction
Reference Document
1 Overview
2 CPU and Interconnect
- 2.1 Event System
- 2.2 System Interconnect and Security (SIS)
- 2.3 Cortex-A7 Processor (Arm)
- 2.4 External Interrupt Controller (EIC)
- 2.5 Debug and Test
- 2.6 NIC-400 Global Programmer’s View (NICGPV)
- 2.7 Bus Matrix (MATRIX)
- 2.8 DMA Controller (XDMAC)
- 2.9 Boot Strategies
  - 2.9.1 Standard Boot Strategy
    - 2.9.1.1 Overview
    - 2.9.1.2 Flow Diagram
    - 2.9.1.3 Chip Setup
    - 2.9.1.4 Standard Boot Configuration
      - 2.9.1.4.1 Default Boot Sequence
      - 2.9.1.4.2 Boot Configuration Packet
      - 2.9.1.4.3 Boot Sequence Controller Configuration Register
        Boot Sequence Controller Configuration Register
      - 2.9.1.4.4 Boot Configuration User Interface
      - 2.9.1.4.5 Monitor Disable
        Monitor Disable
      - 2.9.1.4.6 Console Pin Muxing
        Console Pin Muxing
      - 2.9.1.4.7 QSPI Memory Configuration Data (First Word)
        QSPI Memory Configuration Data (First Word)
      - 2.9.1.4.8 QSPI Memory Configuration Data (Second Word)
        QSPI Memory Configuration Data (Second Word)
      - 2.9.1.4.9 SDMMC Memory Configuration Data (First Word)
        SDMMC Memory Configuration Data (First Word)
      - 2.9.1.4.10 SDMMC Memory Configuration Data (Second Word)
        SDMMC Memory Configuration Data (Second Word)
      - 2.9.1.4.11 NVM Boot Sequence
      - 2.9.1.4.12 Valid Code Detection
      - 2.9.1.4.13 Detailed Memory Boot Procedures
        2.9.1.4.13.1 SD Card/e.MMC Boot
        2.9.1.4.13.2 SPI Flash Boot
        2.9.1.4.13.3 QSPI NOR Flash Boot
      - 2.9.1.4.14 Hardware and Software Constraints
    - 2.9.1.5 Standard Monitor
  - 2.9.2 Secure Boot Strategy
  - 2.9.3 Key Provisioning and Bootstrap Programming
3 Memories
4 System Controller
5 Analog Subsystem
6 Image Subsystem
7 Audio Subsystem
8 Security and Cryptography Subsystem
9 Connectivity Subsystem
10 USB Subsystem
11 Electrical and Mechanical Characteristics
12 Glossary
13 Revision History
Microchip Information