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Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security
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SAMA7G54
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3
Memories
3.2
Static Memory Controller (SMC)
3.2.19
Software Implementation
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
3.1
Overview
3.2
Static Memory Controller (SMC)
3.2.1
Description
3.2.2
Embedded Characteristics
3.2.3
Block Diagram
3.2.4
I/O Lines Description
3.2.5
Multiplexed Signals
3.2.6
Application Example
3.2.7
Product Dependencies
3.2.8
External Memory Mapping
3.2.9
Connection to External Devices
3.2.10
Standard Read and Write Protocols
3.2.11
Scrambling/Unscrambling Function
3.2.12
Automatic Wait States
3.2.13
Data Float Wait States
3.2.14
External Wait
3.2.15
Slow Clock Mode
3.2.16
Register Write Protection
3.2.17
NFC Operations
3.2.18
PMECC Controller Functional Description
3.2.19
Software Implementation
3.2.19.1
Remainder Substitution Procedure
3.2.19.2
Finding the Error Location Polynomial Sigma(x)
3.2.19.3
Finding the Error Position
3.2.20
Register Summary
3.3
Universal DDR Memory Controller (UDDRC)
3.4
DDR/LPDDR Physical Interface (DDR3PHY)
4
System Controller
5
Analog Subsystem
6
Image Subsystem
7
Audio Subsystem
8
Security and Cryptography Subsystem
9
Connectivity Subsystem
10
USB Subsystem
11
Electrical and Mechanical Characteristics
12
Glossary
13
Revision History
Microchip Information
3.2.19 Software Implementation
