2.2.2 System Interconnect Overview

The following table shows allowed paths (X).

Table 2-7. System Interconnections
UDDRC_P0 – MCK4UDDRC_P1 – MCK1UDDRC_P2 – MCK1UDDRC_P3 – MCK3UDDRC_P4 – MCK1OTPC – MCK0CPKCC RAM/ROM – MCK0APB0 – MCK0APB1 – MCK1APB2 – MCK1APB3 – MCK1APB4 – MXK1APB5 – MCK1APB6 – MCK1APB7 – MCK1USB_RAM – MCK1SRAM_P0 – MCK1SRAM_P1 – MCK1TZAESB – MCK1SMC – MKC1QSPI0 – MCK1QSPI1 – MCK1NFC_RAM – MCK1NFC_CMD – MCK1UHPHS_OHCI/EHCI – MCK1APB_DBG/APB_DBG_S – MCK1NICGPV – MCK1CSI2DC_META – MCK1ROM/ ECC_ROM – MCK0
TrustZone Management Location(1)TZCTZCTZCTZCTZCAS(2)AS (2)AS(2)TZPMTZPMTZPMTZPMTZPMTZPMTZPMMATRIXMATRIXMATRIXTZAESBAS -CTZPMMATRIXMATRIXMATRIXMATRIXMATRIXMATRIXMATRIXAS(2)MCK1MCK0
CA7 – MCK4Supervi-sor mode or CP15XXXXXXXXXXXXXXXXXXXXXXX
XDMAC0–MCK1XDMAC0XXXXXXXXXXXX
XDMAC1–MCK1XDMAC1XXXXXXXXXXXX
GMAC0–MCK1TZPMXXXXX
GMAC1–MCK1TZPMXXXXX
SDMMC0–MCK1TZPMXXXXX
SDMMC1–MCK1TZPMXXXXX
SDMMC2–MCK1TZPMXXXXX
XDMAC2–MCK1XDMAC2XXXXXXXX
MCAN0 – MCK1TZPMX
MCAN1–MCK1TZPMX
MCAN2–MCK1TZPMX
MCAN3–MCK1TZPMX
MCAN4–MCK1TZPMX
MCAN5–MCK1TZPMX
ICM–MCK1TZPMXXXXX
UDPHS0_DMA–MCK1TZPMXX
UDPHS1_DMA–MCK1TZPMXX
OHCI_DMA – MCK1TZPMXX
EHCI_DMA–MCK1TZPMXX
TZAESB–MCK1TZAESBASCXXXXX
ISC–MCK3TZPMX
Note:
  1. Refer to the following sections for details on each configuration method.
  2. “AS” stands for Always Secure; this configuration cannot be changed.