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SAMA7G54
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4
System Controller
4.11
OTP Memory Controller (OTPC)
4.11.5
Functional Description
4.11.5.3
User Area
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
4.1
Overview
4.2
System Controller Write Protection (SYSCWP)
4.3
General Purpose Backup Registers (GPBR)
4.4
Dual Watchdog Timer (DWDT)
4.5
Reset Controller (RSTC)
4.6
Real-Time Timer (RTT)
4.7
Real-Time Clock (RTC)
4.8
Shutdown Controller (SHDWC)
4.9
64-bit Periodic Interval Timer (PIT64B)
4.10
Chip Identifier (CHIPID)
4.11
OTP Memory Controller (OTPC)
4.11.1
Description
4.11.2
Embedded Characteristics
4.11.3
Block Diagram
4.11.4
Product Dependencies
4.11.5
Functional Description
4.11.5.1
Bus Interfaces
4.11.5.2
OTP Memory Partitioning
4.11.5.3
User Area
4.11.5.3.1
Area Configuration and Control
4.11.5.3.2
Area Mapping
4.11.5.3.3
Packet Definition
4.11.5.3.4
Init
4.11.5.3.5
Read Access
4.11.5.3.6
Write (Program) Considerations
4.11.5.3.7
Write (Program) Access
4.11.5.3.8
Fixing Corruption
4.11.5.3.9
“Software” Protections
4.11.5.3.10
“Hardware” Protections
4.11.5.4
OTP Emulation Mode
4.11.5.5
Interrupts
4.11.5.6
Register Write Protection
4.11.6
Register Summary
4.12
Special Function Registers (SFR)
4.13
Special Function Registers Backup (SFRBU)
4.14
Slow Clock Controller (SCKC)
4.15
Clock Generator
4.16
Power Management Controller (PMC)
4.17
Parallel Input/Output Controller (PIO)
5
Analog Subsystem
6
Image Subsystem
7
Audio Subsystem
8
Security and Cryptography Subsystem
9
Connectivity Subsystem
10
USB Subsystem
11
Electrical and Mechanical Characteristics
12
Glossary
13
Revision History
Microchip Information
4.11.5.3 User Area
