Jump to main content
Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security
Search
Product Pages
SAMA7G54
Home
8
Security and Cryptography Subsystem
8.5
Secure Hash Algorithm (SHA)
8.5.4
Functional Description
8.5.4.10
Security Features
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Analog Subsystem
6
Image Subsystem
7
Audio Subsystem
8
Security and Cryptography Subsystem
8.1
Overview
8.2
TrustZone Advanced Encryption Standard Bridge (TZAESB)
8.3
TrustZone AES Bridge Address Space Controller (TZAESBASC)
8.4
Advanced Encryption Standard (AES)
8.5
Secure Hash Algorithm (SHA)
8.5.1
Description
8.5.2
Embedded Characteristics
8.5.3
Product Dependencies
8.5.4
Functional Description
8.5.4.1
SHA Algorithm
8.5.4.2
HMAC Algorithm
8.5.4.3
Processing Period
8.5.4.4
Double Input Buffer
8.5.4.5
Internal Registers for Initial Hash Value or Expected Hash Result
8.5.4.6
Automatic Padding
8.5.4.7
Automatic Check
8.5.4.8
Protocol Layers Improved Performances
8.5.4.9
Start Modes
8.5.4.10
Security Features
8.5.4.10.1
Unspecified Register Access Detection
8.5.4.10.2
Register Write Protection
8.5.4.10.3
Security and Safety Analysis and Reports
8.5.5
Register Summary
8.6
Triple Data Encryption Standard (TDES)
8.7
Random Number Generator (TRNG)
8.8
Integrity Check Monitor (ICM)
8.9
Classical Public Key Cryptography Controller (CPKCC)
8.10
Security Module (SECUMOD)
9
Connectivity Subsystem
10
USB Subsystem
11
Electrical and Mechanical Characteristics
12
Glossary
13
Revision History
Microchip Information
8.5.4.10 Security Features
