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SAMA7G54
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3
Memories
3.3
Universal DDR Memory Controller (UDDRC)
3.3.5
Functional Description
3.3.5.11
High-Level SDRAM Initialization Procedure
3.3.5.11.11
Step 10
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
3.1
Overview
3.2
Static Memory Controller (SMC)
3.3
Universal DDR Memory Controller (UDDRC)
3.3.1
Description
3.3.2
Embedded Characteristics
3.3.3
Block Diagram
3.3.4
I/O Lines Description
3.3.5
Functional Description
3.3.5.1
AXI Port Interface (XPI)
3.3.5.2
Port Arbiter (PA)
3.3.5.3
Address Mapper
3.3.5.4
Address Collision Handling
3.3.5.5
Quality of Service (QoS)
3.3.5.6
Bypass Operation
3.3.5.7
Burst Mode Operation
3.3.5.8
Refresh Controls
3.3.5.9
ZQ Calibration
3.3.5.10
ODT Control
3.3.5.11
High-Level SDRAM Initialization Procedure
3.3.5.11.1
Global Configuration
3.3.5.11.2
Step 1
3.3.5.11.3
Step 2
3.3.5.11.4
Step 3
3.3.5.11.5
Step 4
3.3.5.11.6
Step 5
3.3.5.11.7
Step 6
3.3.5.11.8
Step 7
3.3.5.11.9
Step 8
3.3.5.11.10
Step 9
3.3.5.11.11
Step 10
3.3.5.11.12
Step 11
3.3.5.11.13
Step 12
3.3.5.11.14
Step 13
3.3.5.11.15
Step 14
3.3.5.11.16
Step 15
3.3.5.11.17
Step 16
3.3.5.12
Mode Register Reads and Writes
3.3.5.13
2T Memory Command Timing
3.3.5.14
Power Saving Features
3.3
Register Summary
3.4
DDR/LPDDR Physical Interface (DDR3PHY)
4
System Controller
5
Analog Subsystem
6
Image Subsystem
7
Audio Subsystem
8
Security and Cryptography Subsystem
9
Connectivity Subsystem
10
USB Subsystem
11
Electrical and Mechanical Characteristics
12
Glossary
13
Revision History
Microchip Information
3.3.5.11.11 Step 10
Wait until UDDRC_STAT.OPERATING MODE changes to 0x1.
