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Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security
Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security
Product Pages
SAMA7G54
  1. Home
  2. 4 System Controller
  3. 4.17 Parallel Input/Output Controller (PIO)
  4. 4.17.5 Functional Description
  5. 4.17.5.16 I/O Line Configuration Freeze
  6. 4.17.5.16.2 Software Freeze

  • Introduction
  • Reference Document
  • 1 Overview
  • 2 CPU and Interconnect
  • 3 Memories
  • 4 System Controller
    • 4.1 Overview
    • 4.2 System Controller Write Protection (SYSCWP)
    • 4.3 General Purpose Backup Registers (GPBR)
    • 4.4 Dual Watchdog Timer (DWDT)
    • 4.5 Reset Controller (RSTC)
    • 4.6 Real-Time Timer (RTT)
    • 4.7 Real-Time Clock (RTC)
    • 4.8 Shutdown Controller (SHDWC)
    • 4.9 64-bit Periodic Interval Timer (PIT64B)
    • 4.10 Chip Identifier (CHIPID)
    • 4.11 OTP Memory Controller (OTPC)
    • 4.12 Special Function Registers (SFR)
    • 4.13 Special Function Registers Backup (SFRBU)
    • 4.14 Slow Clock Controller (SCKC)
    • 4.15 Clock Generator
    • 4.16 Power Management Controller (PMC)
    • 4.17 Parallel Input/Output Controller (PIO)
      • 4.17.1 Description
      • 4.17.2 Embedded Characteristics
      • 4.17.3 Block Diagram
      • 4.17.4 Product Dependencies
      • 4.17.5 Functional Description
        • 4.17.5.1 I/O Line Configuration Method
        • 4.17.5.2 Pull-Up and Pull-Down Resistor Control
        • 4.17.5.3 General Purpose or Peripheral Function Selection
        • 4.17.5.4 Output Control
        • 4.17.5.5 Synchronous Data Output
        • 4.17.5.6 Open-Drain Mode
        • 4.17.5.7 Output Line Timings
        • 4.17.5.8 Inputs
        • 4.17.5.9 Input Glitch and Debouncing Filters
        • 4.17.5.10 Input Edge/Level Interrupt
        • 4.17.5.11 Interrupt Management
        • 4.17.5.12 I/O Lines Lock
        • 4.17.5.13 Programmable I/O Drive
        • 4.17.5.14 Programmable Schmitt Trigger
        • 4.17.5.15 Programmable Slew Rate
        • 4.17.5.16 I/O Line Configuration Freeze
          • 4.17.5.16.1 Introduction
          • 4.17.5.16.2 Software Freeze
            • 4.17.5.16.2.1 Physical Freeze
            • 4.17.5.16.2.2 Interrupt Freeze
          • 4.17.5.16.3 Tamper Freeze
        • 4.17.5.17 Register Write Protection
      • 4.17.6 I/O Lines Programming Example
      • 4.17.7 Register Summary
  • 5 Analog Subsystem
  • 6 Image Subsystem
  • 7 Audio Subsystem
  • 8 Security and Cryptography Subsystem
  • 9 Connectivity Subsystem
  • 10 USB Subsystem
  • 11 Electrical and Mechanical Characteristics
  • 12 Glossary
  • 13 Revision History
  • Microchip Information

4.17.5.16.2 Software Freeze

Once the I/O line configuration is done, it can be frozen by using the PIO I/O Freeze Configuration Register (PIO_IOFRx) of the corresponding group or the Secure PIO I/O Freeze Configuration Register (S_PIO_IOFRx) if the I/O line is Secure.

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