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Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security
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Product Pages
SAMA7G54
Introduction
Reference Document
1
Overview
1.1
Features
1.2
Ordering Information
1.3
Product Identification System
1.4
Marking
1.5
Configuration Summary
1.6
Block Diagram
1.7
Signal Description
1.8
Package and Pinout
1.9
Microchip Recommended Power Management Solutions
1.10
Safety and Security Features
1.11
Memory Mapping
1.12
Peripheral Identifiers
2
CPU and Interconnect
2.1
Event System
2.2
System Interconnect and Security (SIS)
2.3
Cortex-A7 Processor (Arm)
2.4
External Interrupt Controller (EIC)
2.5
Debug and Test
2.6
NIC-400 Global Programmer’s View (NICGPV)
2.7
Bus Matrix (MATRIX)
2.8
DMA Controller (XDMAC)
2.9
Boot Strategies
3
Memories
3.1
Overview
3.2
Static Memory Controller (SMC)
3.3
Universal DDR Memory Controller (UDDRC)
3.4
DDR/LPDDR Physical Interface (DDR3PHY)
4
System Controller
4.1
Overview
4.2
System Controller Write Protection (SYSCWP)
4.3
General Purpose Backup Registers (GPBR)
4.4
Dual Watchdog Timer (DWDT)
4.5
Reset Controller (RSTC)
4.6
Real-Time Timer (RTT)
4.7
Real-Time Clock (RTC)
4.8
Shutdown Controller (SHDWC)
4.9
64-bit Periodic Interval Timer (PIT64B)
4.10
Chip Identifier (CHIPID)
4.11
OTP Memory Controller (OTPC)
4.12
Special Function Registers (SFR)
4.13
Special Function Registers Backup (SFRBU)
4.14
Slow Clock Controller (SCKC)
4.15
Clock Generator
4.16
Power Management Controller (PMC)
4.17
Parallel Input/Output Controller (PIO)
5
Analog Subsystem
5.1
Overview
5.2
Analog-to-Digital Converter (ADC) Controller
5.3
Analog Comparator Controller (ACC)
6
Image Subsystem
6.1
Overview
6.2
Camera Serial Interface (CSI)
6.3
CSI-2 Demultiplexer Controller (CSI2DC)
6.4
Image Sensor Controller (ISC)
7
Audio Subsystem
7.1
Overview
7.2
Inter-IC Sound Multi-Channel Controller (I2SMCC)
7.3
Synchronous Serial Controller (SSC)
7.4
Sony/Philips Digital Interface Receiver (SPDIFRX)
7.5
Sony/Philips Digital Interface Transmitter (SPDIFTX)
7.6
Pulse Density Microphone Controller (PDMC)
7.7
Asynchronous Sample Rate Converter (ASRC)
8
Security and Cryptography Subsystem
8.1
Overview
8.2
TrustZone Advanced Encryption Standard Bridge (TZAESB)
8.3
TrustZone AES Bridge Address Space Controller (TZAESBASC)
8.4
Advanced Encryption Standard (AES)
8.5
Secure Hash Algorithm (SHA)
8.6
Triple Data Encryption Standard (TDES)
8.7
Random Number Generator (TRNG)
8.8
Integrity Check Monitor (ICM)
8.9
Classical Public Key Cryptography Controller (CPKCC)
8.10
Security Module (SECUMOD)
9
Connectivity Subsystem
9.1
Overview
9.2
Gigabit
Ethernet MAC (GMAC)
9.3
Flexible Serial Communication Controller (FLEXCOM)
9.4
Quad Serial Peripheral Interface (QSPI)
9.5
Secure Digital MultiMedia Card Controller (SDMMC)
9.6
Controller Area Network (MCAN)
9.7
Timer Counter (TC)
9.8
Pulse Width Modulation Controller (PWM)
10
USB Subsystem
10.1
Overview
10.2
USB Type-C™ Port Controller (TCPC)
10.3
USB 2.0 PHY
10.4
USB Device High Speed Port (UDPHS)
10.5
USB Host High Speed Port (UHPHS)
11
Electrical and Mechanical Characteristics
11.1
Electrical Characteristics
11.2
Mechanical Characteristics
12
Glossary
12.1
Glossary
13
Revision History
13.1
Revision History
Microchip Information
Trademarks
Legal Notice
Microchip Devices Code Protection Feature
