7.3.9.11 SSC FIFO Mode Register

This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.

Name: SSC_FFMR
Offset: 0x28
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
        RXFIFODIS 
Access R/W 
Reset 0 
Bit 15141312111098 
     THRS[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
        TXFIFODIS 
Access R/W 
Reset 0 

Bit 16 – RXFIFODIS Receive FIFO Disable

ValueDescription
0The receive FIFO is enabled.
1The receive FIFO is disabled. Only a single entry Receive Holding register is available instead.

Bits 11:8 – THRS[3:0] Transmit Start Threshold

Number of additional data to be written into SCC_THFR prior to loading the first data into the Transmit Shift register.

0 means the first data written into SCC_THFR is immediately loaded into the Shift register.

7 means the loading into SSC_THFR will occur only when the transmit FIFO is full.

Bit 0 – TXFIFODIS Transmit FIFO Disable

ValueDescription
0The transmit FIFO is enabled.
1The transmit FIFO is disabled. Only a single entry Transmit Holding register is available instead.