7.6.7.8 PDMC Interrupt Status Register

Name: PDMC_ISR
Offset: 0x20
Reset: 0x00000002
Property: Read-only

Bit 3130292827262524 
    WPERR     
Access R 
Reset 0 
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
   RXOVRRXUDRRXCHUNKRXFULLRXEMPTYRXRDY 
Access RRRRRR 
Reset 000010 

Bit 28 – WPERR Write Protect Event Interrupt Status (cleared on read)

To clear this flag, the source of the error must not be active.

ValueDescription
0 No security event has occurred since the last read of PDMC_ISR.
1 One or more security events occurred since the last read of PDMC_ISR. For details on the event(s), see PDMC_WPSR.

Bit 5 – RXOVR Receive Over Flow Interrupt Status (cleared on read)

ValueDescription
0 No overflow event occurred since the last read of PDMC_ISR.
1 At least one overflow event occurred since the last read of PDMC_ISR.

Bit 4 – RXUDR Receive Under Flow Interrupt Status (cleared on read)

ValueDescription
0 No underflow event occurred since the last read of PDMC_ISR.
1 At least one underflow event occurred since the last read of PDMC_ISR.

Bit 3 – RXCHUNK Receive FIFO Chunk Interrupt Status (cleared by reading PDMC_RHR)

ValueDescription
0 There is less than PDMC_MR.CHUNK data in the RX FIFO.
1 At least PDMC_MR.CHUNK data can be read in the RX FIFO.

Bit 2 – RXFULL Receive FIFO Full Interrupt Status (cleared by reading PDMC_RHR)

ValueDescription
0 The RX FIFO is not full and can still receive data.
1 The RX FIFO is full and cannot receive more data.

Bit 1 – RXEMPTY Receive FIFO Empty Interrupt Status (automatically cleared when an audio sample is generated)

ValueDescription
0 At least one data is in the RX FIFO.
1 The RX FIFO is empty.

Bit 0 – RXRDY Receive Ready Interrupt Status (cleared by reading PDMC_RHR)

ValueDescription
0 There is no data in the RX FIFO.
1 At least one data is in the RX FIFO and can be read through PDMC_RHR.