This package contains an exposed paddle that must be connected to the system board
ground. The ATWILC3000-MR110xA module pin assignment is
shown in following figure.Figure 3-1. ATWILC3000-MR110xA Module Pin Assignment
The following table provides the ATWILC3000-MR110xA module pin description.
Connect to VDDIO through a 1 MΩ resistor to enable SPI
interface. Connect to GND to enable SDIO interface
3
NC
—
No connection
4
NC
—
No connection
5
NC
—
No connection
6
NC
—
No connection
7
RESETN
Digital Input
Active-low hard Reset. When this pin is asserted low,
the module is placed in the Reset state. When this pin is asserted high,
the module is out of Reset and functions normally. Connect to a host
output that defaults low on power-up. If the host output is tri-stated,
add a 1 MΩ pull down resistor to ensure a low level at power-up
8
BT_TXD
Digital I/O, Programmable pull up
Bluetooth UART transmits data output. Connect to
UART_RXD of host
9
BT_RXD
Digital I/O, Programmable pull up
Bluetooth UART receives data input. Connect to UART_TXD
of host
10
BT_RTS/I2C_SDA_S
Digital I/O, Programmable pull up
I2C Client data. Used only for debug development purposes.
It is recommended to add a test point for this pin. I2C
will be the default configuration. If flow control is enabled, this
pin will be configured as UART RTS
11
BT_CTS/I2C_SCL_S
Digital I/O, Programmable pull up
I2C Client clock. Used only for debug development
purposes. It is recommended to add a test point for this pin.
I2C will be the default configuration. If flow control is
enabled, this pin will be configured as UART CTS
12
VDDIO
Power
Digital I/O power supply
13
GND
GND
Ground
14
GPIO3
Digital I/O, Programmable pull up
GPIO_3(1)
15
GPIO4
Digital I/O, Programmable pull up
GPIO_4(1)
16
UART_TXD
Digital I/O, Programmable pull up
Wi-Fi® UART TxD output. Used only for debug development
purposes. It is recommended to add a test point for this pin
17
UART_RXD
Digital I/O, Programmable pull up
Wi-Fi UART RxD input. Used only for debug development
purposes. It is recommended to add a test point for this pin
18
VBAT
Power
Power supply pin for DC/DC converter and PA
19
CHIP_EN
Digital Input
PMU enable. High level enables the module and the low
level places the module in Power- Down mode. Connect to a host output
that defaults low at power-up. If the host output is tri-stated, add a 1
MΩ pull down resistor if necessary to ensure a low level at
power-up
20
RTC_CLK
Digital I/O, Programmable pull up
RTC Clock input. Connect to a 32.768 kHz clock
source
21
GND
GND
Ground
22
SD_CLK/GPIO8
Digital I/O, Programmable pull up
SDIO clock line from the ATWILC3000-MR110xA, when the module is configured for
SDIO
23
SD_CMD/SPI_SCK
Digital I/O, Programmable pull up
SDIO CMD line from ATWILC3000-MR110xA, when the module is configured for SDIO.
SPI clock from ATWILC3000-MR110xA, when
the module is configured for SPI
24
SD_DAT0/SPI_MISO
Digital I/O, Programmable pull up
SDIO Data Line 0 from the ATWILC3000-MR110xA, when the module is configured for SDIO.
SPI MISO (Host In Client Out) pin from the ATWILC3000-MR110xA, when the module is configured for
SPI
25
SD_DAT1/SPI_SSN
Digital I/O, Programmable pull up
SDIO Data Line 1 from the ATWILC3000-MR110xA, when the module is configured for SDIO.
Active-low SPI SSN (Client Select) pin from the ATWILC3000-MR110xA, when the module is configured for
SPI
26
SD_DAT2/SPI_MOSI
Digital I/O, Programmable pull up
SDIO Data Line 2 from the ATWILC3000-MR110xA, when the module is configured for SDIO.
SPI MOSI (Host Out Client In) pin from the ATWILC3000-MR110xA, when the module is configured for
SPI
27
SD_DAT3/GPIO7
Digital I/O, Programmable pull up
SDIO Data Line 3 from the ATWILC3000-MR110xA, when the module is configured for
SDIO
28
GND
GND
Ground
29
GPIO17
Digital I/O, Programmable pull up
GPIO_17(1)
30
GPIO18
Digital I/O, Programmable pull up
GPIO_18(1)
31
GPIO19
Digital I/O, Programmable pull up
GPIO_19(1)
32
GPIO20
Digital I/O, Programmable pull up
GPIO_20(1)
33
IRQN
Digital output, Programmable pull up
ATWILC3000-MR110xA module
interrupt output. Connect to a host interrupt pin
34
GPIO 21
Digital I/O, Programmable pull up
GPIO_21(1)
35
GPIO 0
Digital I/O, Programmable pull up
GPIO_0(1)
36
GND
GND
Ground
37
PADDLE VSS
Power
Connect to the system board ground
Note:
Usage of the GPIO
functionality is not supported by the firmware. The data sheet will be
updated once the support for this feature is added.