4.5 Radio Subsystem
The ATSAMA5D27-WLSOM1 embeds an ATWILC3000-MR110UA module, which uses a single chip IEEE 802.11 b/g/n RF/Baseband/MAC link controller and Bluetooth 5. The ATWILC3000 connects to Microchip MPUs, with minimal resource requirements with simple SDIO-to-Wi-Fi and UART-to-Bluetooth interfaces.
The ATWILC3000-MR110UA supports single stream 1x1 802.11n mode, providing tested throughput of up to 46 Mbps UDP & 28 Mbps TCP/IP. The ATWILC3000-MR110UA features fully integrated power amplifier, LNA, switch and power management. Implemented in low-power CMOS technology, the ATWILC3000-MR110UA offers very low power consumption while simultaneously providing high performance and minimal bill of materials.
The ATWILC3000-MR110UA utilizes highly -optimized 802.11 Bluetooth coexistence protocols. The only external clock sources needed are a high-speed crystal or oscillator and a 32.768 kHz clock for sleep operation. In the ATSAMA5D27-WLSOM1, the 32.768 kHz clock is provided by the ATSAMA5D27 through PB13.
For more information, refer to the product web page.
| Power Rail | I/O Type | Primary | Alternate | PIO Peripheral | Reset State | Note | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| Signal | Type | Signal | Dir | Func | Signal | Dir | IO Set | Signal, Dir, PU, PD, HiZ, ST, SEC, FILTER | |||
| VDD_3V3 | GPIO | PA18 | I/O | – | – | E | SDMMC1_DAT0 | I/O | 1 | PIO, I, PU, ST | Used for SDIO Interface |
| VDD_3V3 | GPIO | PA19 | I/O | – | – | E | SDMMC1_DAT1 | I/O | 1 | PIO, I, PU, ST | |
| VDD_3V3 | GPIO | PA20 | I/O | – | – | E | SDMMC1_DAT2 | I/O | 1 | PIO, I, PU, ST | |
| VDD_3V3 | GPIO | PA21 | I/O | – | – | E | SDMMC1_DAT3 | I/O | 1 | PIO, I, PU, ST | |
| VDD_3V3 | GPIO | PA22 | I/O | – | – | E | SDMMC1_CK | I/O | 1 | PIO, I, PU, ST | |
| VDD_3V3 | GPIO | PA28 | I/O | – | – | E | SDMMC1_CMD | I/O | 1 | PIO, I, PU, ST | |
| VDD_3V3 | GPIO | PA23 | I/O | – | – | A | FLEXCOM1_IO1 | I/O | 1 | PIO, I, PU, ST | Used for USART Interface |
| VDD_3V3 | GPIO | PA24 | I/O | – | – | A | FLEXCOM1_IO0 | I/O | 1 | PIO, I, PU, ST | |
| VDD_3V3 | GPIO | PA25 | I/O | – | – | A | FLEXCOM1_IO3 | O | 1 | PIO, I, PU, ST | |
| VDD_3V3 | GPIO | PA26 | I/O | – | – | A | FLEXCOM1_IO4 | O | 1 | PIO, I, PU, ST | |
| VDD_3V3 | GPIO | PA27 | I/O | – | – | – | PA27 | O | – | PIO, I, PU, ST | WILC Reset Line |
| VDD_3V3 | GPIO | PA29 | I/O | – | – | – | PA29 | O | – | PIO, I, PU, ST | WILC Chip Select |
| VDD_3V3 | GPIO | PB13 | I/O | – | – | – | PCK1 | O | 3 | PIO, I, PU, ST | WILC 32 kHz |
| VDD_3V3 | GPIO | PB25 | I/O | – | – | – | PB25 | I | – | PIO, I, PU, ST | WILC Interrupt |