4.3.1 Ethernet Phy
The Microchip ATSAMA5D27-WLSOM1 embeds a single-supply 10Base-T/100Base-TX Ethernet physical layer transceiver for transmission and reception of data over a standard CAT-5 unshielded twisted pair (UTP) cable.
The KSZ8081RNAIA is a highly-integrated PHY solution. The KSZ8081RNAIA offers the Reduced Media Independent Interface (RMII) for direct connection to RMII-compliant MACs in Ethernet processors.
A small size MEMS Oscillator (DSC6102HI2B-025.0000) of 25-MHz is used to generate the clock source of the Ethernet functionalities of the SAMA5D27 MPU. This functionality is controlled internally by the MPU GPIO, PD24.
The KSZ8081RNAIA is available in 24-pin, lead-free QFN packages. For more information, refer to the product web page.
| Power Rail | I/O Type | Primary | Alternate | PIO Peripheral | Reset State | Note | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| Signal | Type | Signal | Dir | Func | Signal | Dir | IO Set | Signal, Dir, PU, PD, HiZ, ST, SEC, FILTER | |||
| VDD_3V3 | GPIO | PB14 | I/O | – | – | F | GTXCK | O | 3 | PIO, I, PU, ST | Used for RMII Interface |
| VDD_3V3 | GPIO | PB15 | I/O | – | – | F | GTXEN | O | 3 | PIO, I, PU, ST | |
| VDD_3V3 | GPIO | PB16 | I/O | – | – | F | GRXDV | I | 3 | PIO, I, PU, ST | |
| VDD_3V3 | GPIO | PB17 | I/O | – | – | F | GRXER | I | 3 | PIO, I, PU, ST | |
| VDD_3V3 | GPIO | PB18 | I/O | – | – | F | GRX0 | I | 3 | PIO, I, PU, ST | |
| VDD_3V3 | GPIO | PB19 | I/O | – | – | F | GRX1 | I | 3 | PIO, I, PU, ST | |
| VDD_3V3 | GPIO | PB20 | I/O | – | – | F | GTX0 | O | 3 | PIO, I, PU, ST | |
| VDD_3V3 | GPIO | PB21 | I/O | – | – | F | GTX1 | O | 3 | PIO, I, PU, ST | |
| VDD_3V3 | GPIO | PB22 | I/O | – | – | F | GMDC | O | 3 | PIO, I, PU, ST | PIO, I, PU, ST |
| VDD_3V3 | GPIO | PB23 | I/O | – | – | F | GMDIO | I/O | 3 | PIO, I, PU, ST | PIO, I, PU, ST |
| VDD_3V3 | GPIO | PB24 | I/O | – | – | – | PB24 | PIO, I, PU, ST | Interrupt Line | ||