Data Sheet Revision History
| Revision Level & Date | Section/Figure/Entry | Correction |
|---|---|---|
| DS60001573J (Mar-2025) | 1.1 | Added SSD (Start-of-Stream Delimiter) Corrected alphabetical order of entries |
| 1.4 | Updated reference documents Corrected links to reference documents | |
| 2.1 | Updated reference to IEEE 802.3 Added reference to RMII patent number | |
| 2.3 | Clarified power supply isolation when sleep mode is not required | |
| 3.4 | Clarified behavior of pins during reset | |
| 3.5.1 | Clarified MODE strap pin requirements for LAN8670 and LAN8672 (Datasheet Clarification d6) | |
| 4.7.2 | Clarified section to show that REFCLKIN is not required prior to reset, only after reset for device to function | |
| 4.8 | Corrected register name and bit name | |
| Fig. 4-10 | Corrected direction of MDC line | |
| 4.12.3, Fig. 4-9, | Correct start of delay measurement for PTP timestamping | |
| 4.14 | Clarified that SQI can be taken over all received data | |
| 4.15 | Added info about cable fault diagnostics algorithm. | |
| 5.1.3, 5.1.4 | Reworded OUI description | |
| 5.1, 5.2, 5.3, 5.4 | Modified wording for reserved register access | |
| 5.1.7 | Explained bitfield MITYP is only valid for LAN8670 (Datasheet Clarification d7), plus minor wording changes to improve clarity. | |
| 5.4.8 | Fixed a typo incorrectly sating the wrong voltage | |
| 5.4.35 | Corrected width of bit-fields | |
| 5.4.48 | Removed bits 3 and 4, which were erroneously included | |
| 6.6 | Added PLCA Collision Detection | |
| Fig. 6-9 - 6-18 | Updated figures to show that the schematic is not dependent on silicon revision | |
| DS60001573H (Dec-2023) | Update for silicon revision 5 (product revision C2) | |
| 6.4 | Clarify Power Connectivity | |
| 3.4, 4.7.2, 7.1, 7.2, 7.5, 7.6.7, 7.7.2 | Clarify REFCLKIN 1.8V/3.3V support and duty cycle range | |
| 3.4, 3.5 | Clarify need for configuration strap pull-up/down resistors | |
| DS60001573G (Jul-2023) | All | Update for silicon revision 4 (product revision C1) |
| DS60001573F (Jun-2023) | All | Update for silicon revision 4 (product revision C1) |
| DS60001573C (Jun-2021) | 3 | Separating unused pins that are internally connected (DNC) from those which are internally unconnected (NC) |
| 7.5 | Updated VIS-VDDP input hysteresis; VO-VDDP, VOH-VDDP output high level drive currents; ICLK input voltage limits | |
| 7.6.2 | Updated typical rise/fall times | |
| 7.6.6 | Updated MII TXD/TXEN setup time | |
| 7.6.7 | Updated RMII RXD/RXER/CRSDV output valid time | |
| 7.7 | Updated 10BASE-T1S PMA Electrical Characteristics | |
| 7.1 | Updated ESD Machine Model rating | |
| 4.7 | Added initialization and configuration sequence | |
| 4.9.2 | Added PLCA diagnostics | |
| 6.6 | Added reference schematics | |
| All | Various editorial changes | |
| DS60001573B (Feb-2021) | All | Updated Release for RevB1 |
| DS60001573A (Aug-2019) | All | Initial Release |