6.8 Reference Schematics

The schematics on the following pages contain example reference implementations of the LAN8670/1/2.

The bus interface network, or BIN, not shown, is composed of the discrete analog components that interface the device TRXP/TRXN pins to the bus connector. Design of the BIN is largely dependent upon specific application requirements, but at a minimum must include a series 100 nF coupling capacitor on each of the TRXP and TRXN pins. Additional bus interface network details are contained in a separate LAN86xx Bus Interface Network (BIN) Reference Design Application Note AN1718.

Figure 6-9. LAN8670 MII Reference Schematic (No Sleep/Wake)

Figure 6-10. LAN8670 MII Reference Schematic (With Sleep/Wake)

Figure 6-11. LAN8670 SC-MII Reference Schematic (No Sleep/Wake)

Figure 6-12. LAN8670 SC-MII Reference Schematic (With Sleep/Wake)

Figure 6-13. LAN8670 RMII Reference Schematic (No Sleep/Wake)

Figure 6-14. LAN8670 RMII Reference Schematic (With Sleep/Wake)

Figure 6-15. LAN8671 RMII Reference Schematic (No Sleep/Wake)

Figure 6-16. LAN8671 RMII Reference Schematic (With Sleep/Wake)

Figure 6-17. LAN8672 MII Reference Schematic (No Sleep/Wake)

Figure 6-18. LAN8672 MII Reference Schematic (With Sleep/Wake)