ATtiny3216/3217

5.1 Multiplexed Signals

Table 5-1. PORT Function Multiplexing
VQFN 24-Pin	SOIC 20-Pin	Pin Name ^(1,2)	Other/Special	ADC0	ADC1	PTC⁽⁴⁾	AC0	AC1	AC2	DAC0	USART0	SPI0	TWI0	TCA0	TCBn	TCD0	CCL
23	16	PA0	RESET/ UPDI	AIN0													LUT0-IN0
24	17	PA1		AIN1							TxD⁽³⁾	MOSI	SDA⁽³⁾				LUT0-IN1
1	18	PA2	EVOUT0	AIN2							RxD⁽³⁾	MISO	SCL⁽³⁾				LUT0-IN2
2	19	PA3	EXTCLK	AIN3							XCK⁽³⁾	SCK		WO3	TCB1 WO
3	20	GND
4	1	V_DD
5	2	PA4		AIN4	AIN0	X0/Y0					XDIR⁽³⁾	SS		WO4		WOA	LUT0-OUT
6	3	PA5	VREFA	AIN5	AIN1	X1/Y1	OUT	AINN0						WO5	TCB0 WO	WOB
7	4	PA6		AIN6	AIN2	X2/Y2	AINN0	AINP1	AINP0	OUT
8	5	PA7		AIN7	AIN3	X3/Y3	AINP0	AINP0	AINN0								LUT1-OUT
9		PB7			AIN4			AINN1	AINP3
10		PB6			AIN5		AINP3		AINN1
11	6	PB5	CLKOUT	AIN8		X12/Y12	AINP1		AINP2					WO2⁽³⁾
12	7	PB4		AIN9		X13/Y13	AINN1	AINP3						WO1⁽³⁾			LUT0-OUT⁽³⁾
13	8	PB3	TOSC1					OUT			RxD			WO0⁽³⁾
14	9	PB2	TOSC2, EVOUT1						OUT		TxD			WO2
15	10	PB1		AIN10		X4/Y4	AINP2				XCK		SDA	WO1
16	11	PB0		AIN11		X5/Y5		AINP2	AINP1		XDIR		SCL	WO0
17	12	PC0			AIN6	X6/Y6						SCK⁽³⁾			TCB0 WO⁽³⁾	WOC
18	13	PC1			AIN7	X7/Y7						MISO⁽³⁾				WOD	LUT1-OUT⁽³⁾
19	14	PC2	EVOUT2		AIN8	X8/Y8						MOSI⁽³⁾
20	15	PC3			AIN9	X9/Y9						SS⁽³⁾		WO3⁽³⁾			LUT1-IN0
21		PC4			AIN10	X10/Y10								WO4⁽³⁾	TCB1 WO⁽³⁾		LUT1-IN1
22		PC5			AIN11	X11/Y11								WO5⁽³⁾			LUT1-IN2

Note:

Pin names are of type Pxn, with x being the PORT instance (A, B) and n the pin number. The notation for signals is PORTx_PINn. All pins can be used as event input.
All pins can be used for external interrupt, where pins Px2 and Px6 of each port have full asynchronous detection.
Alternate pin positions. For selecting the alternate positions, refer to section 15 PORTMUX - Port Multiplexer.
Every PTC line can be configured as X- or Y-line.

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