25.5.1 Control A
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DORD | MASTER | CLK2X | PRESC[1:0] | ENABLE | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bit 6 – DORD Data Order
| Value | Description |
|---|---|
| 0 | The MSb of the data word is transmitted first |
| 1 | The LSb of the data word is transmitted first |
Bit 5 – MASTER Master/Slave Select
This bit selects the desired SPI mode.
If SS is configured as input and driven low
while this bit is ‘1’, then this bit is cleared and the IF in
SPIn.INTFLAGS is set. The user has to write MASTER = 1 again to
re-enable SPI Master mode.
This behavior is controlled by the Slave Select Disable (SSD) bit in SPIn.CTRLB.
| Value | Description |
|---|---|
| 0 | SPI Slave mode selected |
| 1 | SPI Master mode selected |
Bit 4 – CLK2X Clock Double
When this bit is written to ‘1’ the SPI speed (SCK
frequency, after internal prescaler) is doubled in Master mode.
| Value | Description |
|---|---|
| 0 | SPI speed (SCK frequency) is not doubled |
| 1 | SPI speed (SCK frequency) is doubled in Master mode |
Bits 2:1 – PRESC[1:0] Prescaler
This bit field controls the SPI clock rate configured in Master mode. These bits have no effect in Slave mode. The relationship between SCK and the peripheral clock frequency (fCLK_PER) is shown below.
The output of the SPI prescaler can be doubled by writing the CLK2X bit to ‘1’.| Value | Name | Description |
|---|---|---|
| 0x0 | DIV4 | CLK_PER/4 |
| 0x1 | DIV16 | CLK_PER/16 |
| 0x2 | DIV64 | CLK_PER/64 |
| 0x3 | DIV128 | CLK_PER/128 |
Bit 0 – ENABLE SPI Enable
| Value | Description |
|---|---|
| 0 | SPI is disabled |
| 1 | SPI is enabled |