21.5.5 Interrupt Flags

Name: INTFLAGS
Offset: 0x06
Reset: 0x00
Property: -

Bit 76543210 
        CAPT 
Access R/W 
Reset 0 

Bit 0 – CAPT Capture Interrupt Flag

This bit is set when a capture interrupt occurs. The interrupt conditions are dependent on the Counter Mode (CNTMODE) bit field in the Control B (TCBn.CTRLB) register.

This bit is cleared by writing a ‘1’ to it or when the Capture register is read in Capture mode.

Table 21-6. Interrupt Sources Set Conditions by Counter Mode
Counter ModeInterrupt Set ConditionTOP ValueCAPT
Periodic Interrupt modeSet when the counter reaches TOPCCMPCNT == TOP
Timeout Check modeSet when the counter reaches TOP
Single-Shot modeSet when the counter reaches TOP
Input Capture Frequency Measurement modeSet on edge when the Capture register is loaded and the counter restarts; the flag clears when the capture is read--On Event, copy CNT to CCMP, and restart counting (CNT == BOTTOM)
Input Capture on Event modeSet when an event occurs and the Capture register is loaded; the flag clears when the capture is readOn Event, copy CNT to CCMP, and continue counting
Input Capture Pulse-Width Measurement modeSet on edge when the Capture register is loaded; the previous edge initialized the count; the flag clears when the capture is read
Input Capture Frequency and Pulse-Width Measurement modeSet on the second edge (positive or negative) when the counter is stopped; the flag clears when the capture is read
8-Bit PWM modeSet when the counter reaches CCMLCCMLCNT == CCML