33.8.7 Interrupt Flag Status and Clear

This flag is cleared by writing ‘1’ to it.

This bit is set when any error is detected. Errors that set this flag have corresponding Status flags in the STATUS register. The BUFOVF error and the LENERR error set this Interrupt flag.

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit clears the flag.

This flag is cleared by writing ‘1’ to it.

This bit is set when a high-to-low transition is detected on the SS pin in Client mode and SPI Select Low Detect (CTRLB.SSDE) is enabled.

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit clears the flag.

This flag is cleared by reading the Data (DATA) register or by disabling the receiver.

This flag is set when there are unread data in the receive buffer. If address matching is enabled, the first data received in a transaction are an address.

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit has no effect.

This flag is cleared by writing ‘1’ to it or by writing new data to DATA.

In Host mode, this flag is set when the data are shifted out and there are no new data in DATA.

In Client mode, this flag is set when the SS pin is pulled high. If address matching is enabled, this flag is only set if the transaction was initiated with an address match.

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit clears the flag.

This flag is cleared by writing new data to DATA.

This flag is set when DATA is empty and ready for new data to transmit.

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit has no effect.