10.12.1 CHECON - Prefetch Module Control Register
| Name: | CHECON |
| Offset: | 0x00 |
| Reset: | 0x0700010F |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ACHEEN | DCHEEN | ICHEEN | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 1 | 1 | 1 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ACHEINV | DCHEINV | ICHEINV | ACHECOH | DCHECOH | ICHECOH | ||||
| Access | R/S/HC | R/S/HC | R/S/HC | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CHEPERF | ADRWS | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PFMSECEN | PREFEN[1:0] | PFMWS[3:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 1 | 1 | 1 | 1 | ||
Bit 26 – ACHEEN Peripheral Data Cache Enable bit
| Value | Description |
|---|---|
| 1 | Caching enabled |
| 0 | Caching disabled (and all lines invalidated) |
Bit 25 – DCHEEN Data Cache Enable bit
| Value | Description |
|---|---|
| 1 | Caching enabled |
| 0 | Caching disabled (and all lines invalidated) |
Bit 24 – ICHEEN Instruction Data Cache Enable bit
| Value | Description |
|---|---|
| 1 | Caching enabled |
| 0 | Caching disabled (and all lines invalidated) |
Bit 22 – ACHEINV Manual Invalidate Control for Peripheral Data Cache
Note: Hardware auto clears this bit when cache
invalidate completes. Bits may clear at different
times.
| Value | Description |
|---|---|
| 1 | Force invalidate cache/invalidate busy |
| 0 | Cache invalidation follows ACHECOH/invalid complete |
Bit 21 – DCHEINV Manual Invalidate Control for Data Cache
Note: Hardware auto clears this bit when cache
invalidate completes. Bits may clear at different
times.
| Value | Description |
|---|---|
| 1 | Force invalidate cache/invalidate busy |
| 0 | Cache invalidation follows DCHECOH/invalid complete |
Bit 20 – ICHEINV Manual Invalidate Control for Instruction Cache
Note:
- Predictive Prefetch Buffer (PFB) is included with iCache invalidate.
- Hardware auto clears this bit when cache invalidate completes. Bits may clear at different times.
| Value | Description |
|---|---|
| 1 | Force invalidate cache/invalidate busy |
| 0 | Cache invalidation follows ICHECOH/invalid complete |
Bit 18 – ACHECOH Auto Cache Coherency Control for Peripheral Data Cache
Note: ACHECOH must be stable before initiation of programming to ensure correct invalidation of data.
| Value | Description |
|---|---|
| 1 | Auto invalidate cache on a programming event |
| 0 | No auto invalidated cache on a programming event |
Bit 17 – DCHECOH Auto Cache Coherency Control for Data Cache
Note: DCHECOH must be stable before initiation of programming to ensure correct invalidation of data.
| Value | Description |
|---|---|
| 1 | Auto invalidate cache on a programming event |
| 0 | No auto invalidated cache on a programming event |
Bit 16 – ICHECOH Auto Cache Coherency Control for Instruction Cache
Note: ICHECOH must be stable before initiation of programming to ensure correct invalidation of data.
| Value | Description |
|---|---|
| 1 | Auto invalidate cache on a programming event |
| 0 | No auto invalidated cache on a programming event |
Bit 12 – CHEPERF Cache Performance Counters Enable
Note: Performance counters are reset on 0 to 1 transition of this bit.
| Value | Description |
|---|---|
| 1 | Enable performance counters |
| 0 | Disable performance counters |
Bit 8 – ADRWS Address Wait State Enable
Note: CPU hang is observed
when CHECON.ADRWS configuration switches from
‘
1’ to ‘0’ and a
Flash read access. To Avoid CPU hangs, execute the
CHECON configuration from SRAM or Boot ROM during
system initialization until the configuration
change is done, then resume execution from Flash
after configuration is set.| Value | Description |
|---|---|
| 1 | Add 1 address Wait state - Allowing for higher clock frequencies |
| 0 | Add 0 address Wait states - Allowing for higher performance at lower clock frequencies |
Bit 7 – PFMSECEN Flash Single-bit Error Corrected (SEC) Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Generate an interrupt when PFMSEC is set |
| 0 | Do not generate an interrupt when PFMSEC is set |
Bits 5:4 – PREFEN[1:0] Instruction Predictive Prefetch Enable
Note: Other values are unavailable.
| Value | Description |
|---|---|
| 01 | Instruction predictive prefetch enabled for cacheable regions only |
| 00 | Instruction predictive prefetch disabled |
Bits 3:0 – PFMWS[3:0] PFM Access Time Defined in Terms of SYSCLK Wait States bits
Note:
- This is not the Wait state seen by the CPU.
- For the Wait states-to-SYSCLK relationship, see Electrical Characteristics from Related Links.
| Value | Description |
|---|---|
| 1111 | Fifteen Wait states |
| 1110 | Fourteen Wait states |
| ... | |
| 0001 | One Wait state |
| 0000 | Zero Wait state |