32.8.1 Control A

Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized

Bit 3130292827262524 
  DORDCPOLCMODEFORM[3:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 2322212019181716 
 SAMPA[1:0]RXPO[1:0]  TXPO[1:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 15141312111098 
 SAMPR[2:0]  RXINVTXINVIBON 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 76543210 
 RUNSTDBY  MODE[2:0]ENABLESWRST 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 30 – DORD Data Order

This bit selects the data order when a character is shifted out from the Data register.

This bit is not synchronized.

ValueDescription
0MSB is transmitted first.
1LSB is transmitted first.

Bit 29 – CPOL Clock Polarity

This bit selects the relationship between data output change and data input sampling in the Synchronous mode.

This bit is not synchronized.

CPOLTxD ChangeRxD Sample
0x0Rising XCK edgeFalling XCK edge
0x1Falling XCK edgeRising XCK edge

Bit 28 – CMODE Communication Mode

This bit selects asynchronous or synchronous communication.

This bit is not synchronized.

ValueDescription
0Asynchronous communication.
1Synchronous communication.

Bits 27:24 – FORM[3:0] Frame Format

These bits define the frame format.

These bits are not synchronized.

FORM[3:0]Description
0x0USART frame
0x1USART frame with parity
0x2LIN Host - Break and sync generation. See LIN Command (CTRLB.LINCMD).
0x3Reserved
0x4Auto-baud (LIN Client) - break detection and auto-baud.
0x5Auto-baud - break detection and auto-baud with parity
0x6Reserved
0x7ISO 7816
0x8-0xFReserved

Bits 23:22 – SAMPA[1:0] Sample Adjustment

These bits define the sample adjustment.

These bits are not synchronized.

SAMPA[1:0]16x Over-sampling (CTRLA.SAMPR=0 or 1)8x Over-sampling (CTRLA.SAMPR=2 or 3)
0x07-8-93-4-5
0x19-10-114-5-6
0x211-12-135-6-7
0x313-14-156-7-8

Bits 21:20 – RXPO[1:0] Receive Data Pinout

These bits define the receive data (RxD) pin configuration.

These bits are not synchronized.

RXPO[1:0]NameDescription
0x0PAD[0]SERCOM PAD[0] is used for data reception
0x1PAD[1]SERCOM PAD[1] is used for data reception
0x2PAD[2]SERCOM PAD[2] is used for data reception
0x3PAD[3]SERCOM PAD[3] is used for data reception

Bits 17:16 – TXPO[1:0] Transmit Data Pinout

These bits define the transmit data (TxD) and XCK pin configurations.

This bit is not synchronized.

TXPOTxD Pin LocationXCK Pin Location (When Applicable)RTS/TECTS
0x0SERCOM PAD[0]SERCOM PAD[1]NANA
0x1Reserved
0x2SERCOM PAD[0]NASERCOM PAD[2]SERCOM PAD[3]
0x3SERCOM_PAD[0]SERCOM_PAD[1]SERCOM_PAD[2]NA

Bits 15:13 – SAMPR[2:0] Sample Rate

These bits select the sample rate.

These bits are not synchronized.

SAMPR[2:0]Description
0x016x over-sampling using arithmetic baud rate generation.
0x116x over-sampling using fractional baud rate generation.
0x28x over-sampling using arithmetic baud rate generation.
0x38x over-sampling using fractional baud rate generation.
0x43x over-sampling using arithmetic baud rate generation.
0x5-0x7Reserved

Bit 10 – RXINV Receive Data Invert

This bit controls whether the receive data (RxD) is inverted or not.
Note: Start, parity and stop bit(s) are unchanged. When enabled, parity is calculated on the inverted data.

This bit is not synchronized.

ValueDescription
0RxD is not inverted.
1RxD is inverted.

Bit 9 – TXINV Transmit Data Invert

This bit controls whether the transmit data (TxD) is inverted or not.
Note: Start, parity and stop bit(s) are unchanged. When enabled, parity is calculated on the inverted data.

This bit is not synchronized.

ValueDescription
0TxD is not inverted.
1TxD is inverted.

Bit 8 – IBON Immediate Buffer Overflow Notification

This bit controls when the Buffer Overflow Status bit (STATUS.BUFOVF) is asserted when a buffer overflow occurs.

This bit is not synchronized.

ValueDescription
0STATUS.BUFOVF is asserted when it occurs in the data stream.
1STATUS.BUFOVF is asserted immediately upon buffer overflow.

Bit 7 – RUNSTDBY Run In Standby

This bit defines the functionality in Standby Sleep mode.

This bit is not synchronized.

RUNSTDBYExternal ClockInternal Clock
0x0External clock is disconnected when ongoing transfer is finished. All reception is dropped.Generic clock is disabled when ongoing transfer is finished. The device will not wake up on Transfer Complete interrupt unless the appropriate ONDEMAND bits are set in the clocking chain.
0x1Wake on Receive Complete interrupt.Generic clock is enabled in all sleep modes. Any interrupt can wake up the device.

Bits 4:2 – MODE[2:0] Operating Mode

These bits select the USART serial communication interface of the SERCOM.

These bits are not synchronized.

ValueDescription
0x0USART with external clock
0x1USART with internal clock

Bit 1 – ENABLE Enable

Due to synchronization, there is a delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE reads back immediately and the Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) is set. SYNCBUSY.ENABLE is cleared when the operation is complete.

This bit is not enable-protected.

ValueDescription
0The peripheral is disabled or being disabled.
1The peripheral is enabled or being enabled.

Bit 0 – SWRST Software Reset

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state and the SERCOM is disabled.

Writing ‘1’ to CTRLA.SWRST always takes precedence, meaning that all other writes in the same write operation are discarded. Any register write access during the ongoing Reset results in an APB error. Reading any register returns the Reset value of the register.

Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the Reset is complete.

This bit is not enable-protected.

ValueDescription
0There is no reset operation ongoing.
1The reset operation is ongoing.