6.4.1.8 Slew Rate Control
Some I/O pins can be configured for various types of slew rate control on their associated port. This is controlled by the slew rate control bits in the SRCON1x and SRCON0x registers that are associated with each I/O port. The slew rate control is configured using the corresponding bit in each register, as shown in the following table.
As an example, writing 0x0001, 0x0000 to SRCON1A and SRCON0A, respectively, can enable slew rate control on the RA0 pin and sets the slew rate to the slow edge rate.
| SRCON1x | SRCON0x | Description |
|---|---|---|
| 1 | 1 | Slew rate control is enabled and is set to the slowest edge rate |
| 1 | 0 | Slew rate control is enabled and is set to the slow edge rate |
| 0 | 1 | Slew rate control is enabled and is set to the medium edge rate |
| 0 | 0 | Slew rate control is disabled and is set to the fastest edge rate |
Note:
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