36.11 ADC Sampling Requirements

The analog input model of the 12-bit ADC is illustrated in the following figure. The total acquisition time for the analog-to-digital conversion is a function of the internal circuit settling time and the holding capacitor charge time.

For the ADC module to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the voltage level on the analog input pin. The analog output source impedance (RS), the interconnect impedance (RIC) and the internal sampling switch (RSS) impedance combine to directly affect the time required to charge the CHOLD. The combined impedance of the analog sources must, therefore, be small enough to fully charge (to within one-fourth LSB of the desired voltage) the holding capacitor within the selected sample time. The internal holding capacitor is in the discharged state prior to each sample operation.

At least 1 TAD7 time period must be allowed between conversions for the acquisition time. See Electrical Characteristics from Related Links.

Figure 36-12. 12-bit ADC Analog Input Model
Note: The CPIN value depends on the device package and is not tested. The effect of the CPIN is negligible if Rs 5 k.
Legend:
  • CPIN = Input capacitance
  • RSS = Sampling switch resistance
  • RS = Source resistance
  • ILEAKAGE = Leakage current at the pin due to various junctions
  • VT = Threshold voltage
  • RIC = Interconnect resistance
  • CHOLD = Sample/hold capacitance