36.13.14 ADCTRG1 – ADC Trigger Source 1 Register
This register controls the trigger source selection for AN0 through AN3 analog inputs.
Name: | ADCTRG1 |
Offset: | 0x1600 |
Reset: | 0x00000000 |
Property: | - |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
TRGSRC3[4:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
TRGSRC2[4:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
TRGSRC1[4:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
TRGSRC0[4:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bits 28:24 – TRGSRC3[4:0] Trigger Source for Conversion of Analog Input AN3 Select bits
Note: For STRIG, in addition to setting the trigger, it also requires programming of the STRGSRC[4:0] bits (ADCCON1[20:16]) to select the trigger source and requires the appropriate CSS bits to be set in the ADCCSSx registers.
Value | Description |
---|---|
10001 - 11111 | Reserved |
10000 | EVSYS_51 |
01111 | EVSYS_50 |
01110 | EVSYS_49 |
01101 | EVSYS_48 |
01100 | EVSYS_47 |
01011 | EVSYS_46 |
01010 | EVSYS_45 |
01001 | EVSYS_44 |
01000 | EVSYS_43 |
00111 | EVSYS_42 |
00110 | EVSYS_41 |
00101 | EVSYS_40 |
00100 | INT0 External interrupt |
00011 | STRIG |
00010 | Global level software trigger (GLSWTRG) |
00001 | Global software edge trigger (GSWTRG) |
00000 | No Trigger |
Bits 20:16 – TRGSRC2[4:0] Trigger Source for Conversion of Analog Input AN2 Select bits
Note: See Bits 28-24 for bit value definitions.
Bits 12:8 – TRGSRC1[4:0] Trigger Source for Conversion of Analog Input AN1 Select bits
Note: See Bits 28-24 for bit value definitions.
Bits 4:0 – TRGSRC0[4:0] Trigger Source for Conversion of Analog Input AN0 Select bits
Note: See Bits 28-24 for bit value definitions.