9.3 High-Speed Bus System
The high-speed bus system matrix connects a multitude of initiator logic cores/IPs to a multitude of target logic cores/IPs, supporting AHB2/APB2 buses.
The high-speed bus system matrix connects a multitude of initiator logic cores/IPs to a multitude of target logic cores/IPs, supporting AHB2/APB2 buses.
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