38.4.3 Clocks

The AC bus clock (PB2_CLK) can be enabled and disabled in the Main Clock module, CRU (see Clock and Reset Unit (CRU) from Related Links), and the Analog Comparator module can be enabled or disabled via the PMD1 register. See Peripheral Module Disable Register (PMD) from Related Links.

A generic clock (GCLK_AC) is required to clock the AC. This clock must be configured and enabled in the generic clock controller before using the AC.

This generic clock is asynchronous to the bus clock (PB2_CLK). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. See Synchronization from Related Links.