41.6.7 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read.

The following bits are synchronized when written:

• Software Reset and Enable bits in Control A register (CTRLA.SWRST and CTRLA.ENABLE)

• Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET)
• Status register (STATUS)
• Pattern and Pattern Buffer registers (PATT and PATTBUF)
• Waveform register (WAVE)
• Count Value register (COUNT)
• Period Value and Period Buffer Value registers (PER and PERBUF)
• Compare/Capture Channel x and Channel x Compare/Capture Buffer Value registers (CCx and CCBUFx)

The following registers are synchronized when read:

• Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET)
• Count Value register (COUNT): synchronization is done on demand through READSYNC command (CTRLBSET.CMD)
• Pattern and Pattern Buffer registers (PATT and PATTBUF)
• Waveform register (WAVE)
• Period Value and Period Buffer Value registers (PER and PERBUF)
• Compare/Capture Channel x and Channel x Compare/Capture Buffer Value registers (CCx and CCBUFx)

Required write synchronization is denoted by the Write-Synchronized property in the register description.

Required read synchronization is denoted by the Read-Synchronized property in the register description.