41.8.16 Waveform

Name: WAVE
Offset: 0x3C
Reset: 0x00000000
Property: Write-Synchronized

Bit 3130292827262524 
      SWAP2SWAP1SWAP0 
Access R/WR/WR/W 
Reset 000 
Bit 2322212019181716 
   POL5POL4POL3POL2POL1POL0 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 15141312111098 
     CICCEN3CICCEN2CICCEN1CICCEN0 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
 CIPEREN RAMP[1:0] WAVEGEN[2:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bits 24, 25, 26 – SWAPx Swap DTI Output Pair x [x=0..2]

Setting these bits enables the output swap of DTI outputs [x] and [x+WO_NUM/2]. Note: the DTIxEN settings will not affect the swap operation.

Bits 16, 17, 18, 19, 20, 21 – POLx Channel Polarity x [x=0..5]

Setting these bits enables the output polarity in single-slope and dual-slope PWM operations.

ValueNameDescription
0(single-slope PWM waveform generation)Compare output is initialized to ~DIR and set to DIR when TCC counter matches CCx value
1(single-slope PWM waveform generation)Compare output is initialized to DIR and set to ~DIR when TCC counter matches CCx value.
0(dual-slope PWM waveform generation)Compare output is set to ~DIR when TCC counter matches CCx value
1(dual-slope PWM waveform generation)Compare output is set to DIR when TCC counter matches CCx value.

Bits 8, 9, 10, 11 – CICCENx Circular CC Enable x [x=0..3]

Setting these bits enables the compare circular buffer option on the first four Compare/Capture channels. When the bit is set, the CCx register value is copied back into the CCBUFx register on the UPDATE condition.

Bit 7 – CIPEREN Circular Period Enable

Setting this bit enables the period circular buffer option. When the bit is set, the PER register value is copied back into the PERBUF register on the UPDATE condition.

Bits 5:4 – RAMP[1:0] Ramp Operation

These bits select the Ramp operation (RAMP). These bits are not synchronized.

ValueNameDescription
0x0RAMP1RAMP1 operation
0x1RAMP2AAlternative RAMP2 operation
0x2RAMP2RAMP2 operation
0x3RAMP2CCritical RAMP2 operation

Bits 2:0 – WAVEGEN[2:0] Waveform Generation Operation

These bits select the waveform generation operation. The settings impact the top value and control if frequency or PWM waveform generation must be used. These bits are not synchronized.

ValueNameDescription
OperationTopUpdate Waveform Output

On Match

Waveform Output

On Update

OVFIF/Event

Up Down

0x0NFRQNormal FrequencyPERTOP/ZeroToggleStableTOPZero
0x1MFRQMatch FrequencyCC0TOP/ZeroToggleStableTOPZero
0x2NPWMNormal PWMPERTOP/ZeroSetClearTOPZero
0x3Reserved
0x4DSCRITICALDual-slope PWMPERZero~DIRStableZero
0x5DSBOTTOMDual-slope PWMPERZero~DIRStableZero
0x6DSBOTHDual-slope PWMPERTOP & Zero~DIRStableTOPZero
0x7DSTOPDual-slope PWMPERZero~DIRStableTOP