41.8.16 Waveform
Name: | WAVE |
Offset: | 0x3C |
Reset: | 0x00000000 |
Property: | Write-Synchronized |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
SWAP2 | SWAP1 | SWAP0 | |||||||
Access | R/W | R/W | R/W | ||||||
Reset | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
POL5 | POL4 | POL3 | POL2 | POL1 | POL0 | ||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
CICCEN3 | CICCEN2 | CICCEN1 | CICCEN0 | ||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CIPEREN | RAMP[1:0] | WAVEGEN[2:0] | |||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 24, 25, 26 – SWAPx Swap DTI Output Pair x [x=0..2]
Setting these bits enables the output swap of DTI outputs [x] and [x+WO_NUM/2]. Note: the DTIxEN settings will not affect the swap operation.
Bits 16, 17, 18, 19, 20, 21 – POLx Channel Polarity x [x=0..5]
Setting these bits enables the output polarity in single-slope and dual-slope PWM operations.
Value | Name | Description |
---|---|---|
0 | (single-slope PWM waveform generation) | Compare output is initialized to ~DIR and set to DIR when TCC counter matches CCx value |
1 | (single-slope PWM waveform generation) | Compare output is initialized to DIR and set to ~DIR when TCC counter matches CCx value. |
0 | (dual-slope PWM waveform generation) | Compare output is set to ~DIR when TCC counter matches CCx value |
1 | (dual-slope PWM waveform generation) | Compare output is set to DIR when TCC counter matches CCx value. |
Bits 8, 9, 10, 11 – CICCENx Circular CC Enable x [x=0..3]
Bit 7 – CIPEREN Circular Period Enable
Setting this bit enables the period circular buffer option. When the bit is set, the PER register value is copied back into the PERBUF register on the UPDATE condition.
Bits 5:4 – RAMP[1:0] Ramp Operation
These bits select the Ramp operation (RAMP). These bits are not synchronized.
Value | Name | Description |
---|---|---|
0x0 | RAMP1 | RAMP1 operation |
0x1 | RAMP2A | Alternative RAMP2 operation |
0x2 | RAMP2 | RAMP2 operation |
0x3 | RAMP2C | Critical RAMP2 operation |
Bits 2:0 – WAVEGEN[2:0] Waveform Generation Operation
These bits select the waveform generation operation. The settings impact the top value and control if frequency or PWM waveform generation must be used. These bits are not synchronized.
Value | Name | Description | ||||||
---|---|---|---|---|---|---|---|---|
Operation | Top | Update | Waveform Output On Match | Waveform Output On Update | OVFIF/Event Up Down | |||
0x0 | NFRQ | Normal Frequency | PER | TOP/Zero | Toggle | Stable | TOP | Zero |
0x1 | MFRQ | Match Frequency | CC0 | TOP/Zero | Toggle | Stable | TOP | Zero |
0x2 | NPWM | Normal PWM | PER | TOP/Zero | Set | Clear | TOP | Zero |
0x3 | Reserved | — | — | — | — | — | — | — |
0x4 | DSCRITICAL | Dual-slope PWM | PER | Zero | ~DIR | Stable | — | Zero |
0x5 | DSBOTTOM | Dual-slope PWM | PER | Zero | ~DIR | Stable | — | Zero |
0x6 | DSBOTH | Dual-slope PWM | PER | TOP & Zero | ~DIR | Stable | TOP | Zero |
0x7 | DSTOP | Dual-slope PWM | PER | Zero | ~DIR | Stable | TOP | — |