33.8.5 Interrupt Enable Clear
| Name: | INTENCLR |
| Offset: | 0x14 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
This register allows the user to disable an interrupt without a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERROR | SSL | RXC | TXC | DRE | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 7 – ERROR Error Interrupt Enable
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit clears the Error Interrupt Enable bit, which disables the Error interrupt.
| Value | Description |
|---|---|
| 0 | Error interrupt is disabled. |
| 1 | Error interrupt is enabled. |
Bit 3 – SSL SPI Select Low Interrupt Enable
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit clears the SPI Select Low Interrupt Enable bit, which disables the SPI Select Low interrupt.
| Value | Description |
|---|---|
| 0 | SPI Select Low interrupt is disabled. |
| 1 | SPI Select Low interrupt is enabled. |
Bit 2 – RXC Receive Complete Interrupt Enable
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit clears the Receive Complete Interrupt Enable bit, which disables the Receive Complete interrupt.
| Value | Description |
|---|---|
| 0 | Receive Complete interrupt is disabled. |
| 1 | Receive Complete interrupt is enabled. |
Bit 1 – TXC Transmit Complete Interrupt Enable
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit clears the Transmit Complete Interrupt Enable bit, which disables the Transmit Complete interrupt.
| Value | Description |
|---|---|
| 0 | Transmit Complete interrupt is disabled. |
| 1 | Transmit Complete interrupt is enabled. |
Bit 0 – DRE Data Register Empty Interrupt Enable
Writing ‘0’ to this bit has no effect.
Writing ‘1’ to this bit clears the Data Register Empty Interrupt Enable bit, which disables the Data Register Empty interrupt.
| Value | Description |
|---|---|
| 0 | Data Register Empty interrupt is disabled. |
| 1 | Data Register Empty interrupt is enabled. |