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SAMA5D2 Series Silicon Errata and Data Sheet Clarification SAMA5D2 Series
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6
Controller Area Network (MCAN)
SAMA5D2 Series
SAMA5D2 Series
1
Silicon Issue Summary
2
Analog Comparator Controller (ACC)
3
Analog-to-Digital Converter (ADC)
4
Audio Class D Amplifier (CLASSD)
5
Audio PLL
6
Controller Area Network (MCAN)
6.1
Flexible data rate feature does not support the ISO 16845-1:2016 CRC
6.2
Needless activation of interrupt MCAN_IR.MRAF
6.3
Return of receiver from Bus Integration state after Protocol Exception Event
6.4
Message RAM/RAM Arbiter not responding in time
6.5
Data loss (payload) in case storage of a received frame has not completed until end of EOF field is reached
6.6
Edge filtering causes mis-synchronization when falling edge at Rx input pin coincides with end of integration phase
6.7
Configuration of MCAN_NBTP.NTSEG2 = ’0’ not allowed
6.8
Retransmission in DAR mode due to lost arbitration at the first two identifier bits
6.9
Tx FIFO message sequence inversion
6.10
Unexpected High Priority Message (HPM) interrupt
6.11
Issue message transmitted with wrong arbitration and control fields
6.12
Debug message handling state machine not reset to Idle state when CCCR.INIT is set
6.13
Frame transmitted despite confirmed transmit cancellation for CAN-FD messages with more than 8 data bytes
7
Ethernet MAC (GMAC)
8
Flexible Serial Communication Controller (FLEXCOM)
9
Inter-IC Sound Controller (I
2
SC)
10
Multiport DDR-SDRAM Controller (MPDDRC)
11
Peripheral Touch Controller (PTC)
12
Power Management Controller (PMC)
13
Pulse Width Modulation Controller (PWM)
14
Quad Serial Peripheral Interface (QSPI)
15
Real-Time Clock (RTC)
16
ROM Code
17
Secure Digital MultiMedia Card Controller (SDMMC)
18
Secure Fuse Controller (SFC)
19
Special Function Registers (SFR)
20
Synchronous Serial Controller (SSC)
21
Two-wire Interface (TWIHS)
22
USB High-Speed Inter-Chip Port (HSIC)
23
Watchdog Timer (WDT)
24
Data Sheet Clarifications
25
Revision History
Microchip Information
6 Controller Area Network (MCAN)
