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SAMA5D2 Series Silicon Errata and Data Sheet Clarification SAMA5D2 Series
SAMA5D2 Series
1 Silicon Issue Summary
2 Analog Comparator Controller (ACC)
2.1 ACC output connection issue
3 Analog-to-Digital Converter (ADC)
3.1 ADC SleepWalking is not functional
3.2 Last channel trigger limitation
3.3 ADC trigger events RTCOUT0 and RTCOUT1 are not functional
4 Audio Class D Amplifier (CLASSD)
4.1 Unexpected offset and noise level in Differential Output mode
5 Audio PLL
5.1 Audio PLL output frequency range
6 Controller Area Network (MCAN)
6.1 Flexible data rate feature does not support the ISO 16845-1:2016 CRC
6.2 Needless activation of interrupt MCAN_IR.MRAF
6.3 Return of receiver from Bus Integration state after Protocol Exception Event
6.4 Message RAM/RAM Arbiter not responding in time
6.5 Data loss (payload) in case storage of a received frame has not completed until end of EOF field is reached
6.6 Edge filtering causes mis-synchronization when falling edge at Rx input pin coincides with end of integration phase
6.7 Configuration of MCAN_NBTP.NTSEG2 = ’0’ not allowed
6.8 Retransmission in DAR mode due to lost arbitration at the first two identifier bits
6.9 Tx FIFO message sequence inversion
6.10 Unexpected High Priority Message (HPM) interrupt
6.11 Issue message transmitted with wrong arbitration and control fields
6.12 Debug message handling state machine not reset to Idle state when CCCR.INIT is set
6.13 Frame transmitted despite confirmed transmit cancellation for CAN-FD messages with more than 8 data bytes
7 Ethernet MAC (GMAC)
7.1 Bad association of timestamps and PTP packets
7.2 Screening registers not working
8 Flexible Serial Communication Controller (FLEXCOM)
8.1 FLEXCOM SMBUS alert signalling is not functional
9 Inter-IC Sound Controller (I2SC)
9.1 I2SC first sent data corrupted
10 Multiport DDR-SDRAM Controller (MPDDRC)
10.1 tFAW timing violation
11 Peripheral Touch Controller (PTC)
11.1 Wrong pull-up value on PD[18:3] during reset
12 Power Management Controller (PMC)
12.1 GCLK fields are reprogrammed unexpectedly
12.2 PMC SleepWalking is not functional
12.3 Change of the field PMC_MCKR.PRES is not allowed if Master/Processor Clock Prescaler frequency is too high
13 Pulse Width Modulation Controller (PWM)
13.1 Fault Protection to Hi-Z for PWMx output not functional
14 Quad Serial Peripheral Interface (QSPI)
14.1 QSPI hangs with long DLYCS
15 Real-Time Clock (RTC)
15.1 RTC_SR.TDERR flag is stuck at 0
15.2 Read access truncated to the first 24 bits for register RTC_TIMALR (UTC_MODE)
16 ROM Code
16.1 Main external clock frequency support for SAM-BA Monitor limitation
16.2 Watchdog reset occurs when reenabling the watchdog
16.3 SPI frequency at bootup is not 11 MHz
16.4 JTAG_TCK on IOSET 4 pin has a wrong configuration after boot
16.5 SDMMC0 and SDMMC1 boot issue
16.6 UART blocks USB connection to SAM-BA Monitor
16.7 Secure Boot Mode: AES-RSA X.509 Certificate Serial Number Length Limit
17 Secure Digital MultiMedia Card Controller (SDMMC)
17.1 Software 'Reset For all' command may not execute properly
17.2 Status flag INTCLKS may not work correctly
17.3 Sampling clock tuning procedure
17.4 SDMMC I/O calibration does not work
18 Secure Fuse Controller (SFC)
18.1 The Partial Fuse Masking function does not work
18.2 The first two bits of each 32-bit block of the fuse matrix cannot be written
18.3 Fuse matrix programming requires a main clock (MAINCK) frequency between 10 and 15 MHz
18.4 Fuse matrix read requires a main clock (MAINCK) frequency below 28 MHz
19 Special Function Registers (SFR)
19.1 The serial number stored in the SFR registers (SFR_SN0 and SFR_SN1) is not correct
20 Synchronous Serial Controller (SSC)
20.1 Unexpected delay on TD output
21 Two-wire Interface (TWIHS)
21.1 The TWI/TWIHS Clear command does not work
22 USB High-Speed Inter-Chip Port (HSIC)
22.1 At HSIC startup, the strobe default state is wrong
23 Watchdog Timer (WDT)
23.1 Restart command of WDT may reset the DDR controller
24 Data Sheet Clarifications
25 Revision History
25.1 Rev. H - 08/2022
25.2 Rev. G - 03/2022
25.3 Rev. F - 09/2021
25.4 Rev. E - 03/2021
25.5 Rev. D - 09/2020
25.6 Rev. C - 02/2020
25.7 Rev. B - 02/2019
25.8 Rev. A - 10/2018
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