2.4.3 Hypothetical Application Example

  • VDDX = (VDDIO, AVDD, VUSB3V3) = 3.3V
  • VDDREG = 1.8V
  • Package = 208-Ball Fine-Pitch Ball Grid Array Package (8MX) - 15x15x1.19 mm Body [TFBGA]
  • 208-Ball Fine-Pitch Ball Grid Array Thermal Resistance θJA = 23.7 °C/W
Figure 2-2. Hypothetical Example of CPU and Active Peripherals Application
Note:
  1. This needs only to be an estimate of application Total IOL sinking current & IOH sourcing current. Determining an exact value for every I/O pins load would be unreasonable.
  2. This value represents only VREG_SWn, (i.e., CORE_IDD) however the CPU IVDDREG spec, (i.e., 255 mA), in the data sheet represents CPU @ 300MHz +SRAM+PLL enabled. For purposes of ensuring VREG_SWn, (i.e., CORE_IDD) load does not exceed 341 mA, therefore: VALUE = (CPU IVDDREG – (SRAM + PLL)) = (255mA - (44 mA+15 mA)) = 196 mA.