18.7.20 PLL1 Post Output Clock Divider A
Important: The PLL1 frequency
cannot be changed on the fly while it's the active enabled clock to the system.
Note: There are two PLL’s, PLL0 &
PLL1 modules, and each has four selectable clock outputs. Two of the four PLL1
output clocks are routed through both of the two fractional divider modules (See
below).
PLL1 Output Clocks:
- CLK_PLL1_FRC_CLKOUTnwhere (n=0).
- CLK_PLL1_FRC_CLKOUTnwhere (n=1).
- CLK_PLL1_CLKOUTn where (n=2).
- CLK_PLL1_CLKOUTn where (n=3).
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | PLL1POSTDIVA |
| Offset: | 0x60 |
| Reset: | 0x20202020 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| OUTEN3 | POSTDIV3[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 1 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| OUTEN2 | POSTDIV2[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 1 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| OUTEN1 | POSTDIV1[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 1 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OUTEN0 | POSTDIV0[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 1 | 0 | 0 | 0 | 0 | 0 | ||
Bits 7, 15, 23, 31 – OUTENn CLK_PLL1_CLKOUTn Output Enable
| Value | Description |
|---|---|
| 0 | CLK_PLL1_CLKOUTn Output Disabled |
| 1 | CLK_PLL1_CLKOUTn Output Enabled |
Bits 0:5, 8:13, 16:21, 24:29 – POSTDIVn PLL1 FVCO Output Clock Division Factor
This field determines the division factor of the PLL1 FVCO output that creates FCLK_PLL1 and CLK_PLL1_CLKOUTn. POSTDIV value must be between 1 ≤ POSTDIV ≤ 63.
Note:
- (FVCO / POSTDIV) > FCLK_PLL1 > CLK_PLL1_CLKOUTn.
- PLL1 must be disabled before making changes to POSTDIVn values.