25.10.2 Channel Control B Register

Note: An attempt to enter a priority higher than the maximum value implemented will write that maximum value instead.

Table 25-16. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CHCTRLBk
Offset:	0x54 + k*0x50 [k=0..15]
Reset:	0x00000000
Property:	PAC Write-Protection, CHCTRLAk.ENABLE =1 write protect


Bit	31	30	29	28	27	26	25	24
	CRCEN		CASTEN			PATEN	PATLEN	PIGNEN
Access	R/W		R/W			R/W	R/W	R/W
Reset	0		0			0	0	0


Bit	23	22	21	20	19	18	17	16
	TRIG[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	BYTORD[1:0]		WBOEN				PR[1:0]
Access	R/W	R/W	R/W				R/W/HS/HC	R/W/HS/HC
Reset	0	0	0				0	0


Bit	7	6	5	4	3	2	1	0
		RAS[2:0]				WAS[2:0]
Access		R/W	R/W	R/W		R/W	R/W	R/W
Reset		0	0	0		0	0	0

Bit 31 – CRCEN CRC Enable Bit

Value	Description
0	CRC module is disabled for this channel and transfers bypass the CRC module
1	CRC module is enabled for this channel and transfers are routed through the CRC module

Bit 29 – CASTEN Cell Auto Start Enable of Ensuing Transfers for this channel.

Value	Description
0	The start of each cell transfer in a block transfer will be delayed until requested by a start trigger.
1	Transfer a complete block of data on a single start trigger event. The first cell transfer will be delayed until requested by an start trigger. Once started it will continue processing additional cells continuously without any additional starting event until a block is finished.

Bit 26 – PATEN Channel Pattern Match Abort Enable

Value	Description
0	Pattern match is disabled
1	Abort transfer and clear CHCTRLAk.ENABLE on pattern match

Bit 25 – PATLEN Pattern Match Length

Value	Description
0	1 byte length
1	2 byte length

Bit 24 – PIGNEN Enable Pattern Ignore Byte

Value	Description
0	Disable this feature.
1	Treat any byte that matches PIGN bits as a don’t care when pattern matching is enabled.

Bits 23:16 – TRIG[7:0] Trigger that can Start a Channel Transfer

If programed to a value greater than the maximum trigger index listed in Table 20-1, all external triggers are disabled. Only software triggering is available.

k= Peripheral request connected, where k is a value from 2 to 90

Value	Description
0	External events disabled, only software trigger can start a transfer.
1	Event system trigger (evsys_dma_chstrt_evt[k]) ifk< 24 otherwise reserved

Bits 15:14 – BYTORD[1:0] Byte Order

Byte swapping takes place prior to sending data into the destination.

Value	Description
11	Bytes Swapped as: 3→2 / 2→3 / 1→0 / 0→1
10	Bytes Swapped as: 3→1 / 2→0 / 1→3 / 0→2
01	Bytes Swapped as: 3→0 / 2→1 / 1→2 / 0→3
00	Unchanged

Bit 13 – WBOEN Write Byte Order Enable

Value	Description
0	Write source data unchanged.
1	Write out data according to BYTORD[1:0].

Bits 9:8 – PR[1:0] Channel Priority Level

Sets the priority level of the channel. Reading back this value returns the current priority level of the channel. If EVAUXACT=1, hardware may adjust the priority level.

Value	Description
11	Channel has priority 4 (highest)
10	Channel has priority 3
01	Channel has priority 2
00	Channel has priority 1

Bits 6:4 – RAS[2:0] Channel Read Address Sequence

Sets the read address and transfer size.

Value	Description
111	Reserved
110	Reserved
101	Fixed address word (32-bit) burst transfer
100	Fixed address of halfword (16-bit) operand (single half-word aligned address)
011	Fixed byte address (single byte address with enable based upon 2 LSBs)
010	Auto increment address and transfer size.
001	Incrementing address +2 with transfers of halfword operands
000	Incrementing address +1 with transfers of byte operands

Bits 2:0 – WAS[2:0] Channel Write Address Sequence

Value	Description
111	Reserved
110	Reserved
101	Fixed address word (32-bit) burst transfer
100	Fixed address of halfword (16-bit) operand (single half-word aligned address)
011	Fixed byte address (single byte address with enable based upon 2 LSBs)
010	Auto increment address and transfer size.
001	Incrementing address +2 with transfers of halfword operands
000	Incrementing address +1 with transfers of byte operands