33.7.13 Event User m

Table 33-15. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: USERm
Offset: 0x0120 + m*0x01 [m=0..116]
Reset: 0x00000000
Property: PAC Write-Protection

Bit 76543210 
   CHANNEL[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bits 5:0 – CHANNEL[5:0] Channel Event Selection

These bits select channel n to connect to the event user m. The following table lists all of the Event Users and the associated 'm' value to determine which USERm register to define the desired Event Channel.

Note:
  1. A value x of this bit field selects channel n = x-1.
  2. By default, a channel is asynchronous. Channel synchronous/resynchronous path can be enabled if its index is < 12 and synchronous/resynchronous selection is written to CHANNEL.PATH bit field.
Table 33-16. Event User Mapping
User MacroUser MultiplexorUSER(m)DescriptionPath Type (1)
FREQMSTART0 -A, R
RTCTAMPER1RTC TamperA
PORTEVx2-5PORT Event x=0..3A, S, R
DMACCHx-Start6-21Channel Start x=0..15A, S, R
DMACCHx-Aux22-37Channel Aux x=0..15A, S, R
TCC0 EVx38-39EV x=0..1A, S, R
MCx40-47MC x=0..7A, S, R
TCC1 EVx48-49EV x=0..1A, S, R
MCx50-57MC x=0..7A, S, R
TCC2 EVx58-59EV x=0..1A, S, R
MCx60-65MC x=0..5A, S, R
TCC3 EVx66-67EV x=0..1A, S, R
MCx68-69MC x=0..1A, S, R
TCC4 EVx70-71EV x=0..1A, S, R
MCx72-73MC x=0..1A, S, R
TCC5 EVx74-75EV x=0..1A, S, R
MCx76-77MC x=0..1A, S, R
TCC6 EVx78-79EV x=0..1A, S, R
MCx80-81MC x=0..1A, S, R
TCC7 EVx82-83EV x=0..1A, S, R
MCx84-85MC x=0..1A, S, R
TCC8 EVx86-87EV x=0..1A, S, R
MCx88-89MC x=0..1A, S, R
TCC9 EVx90-91EV x=0..1A, S, R
MCx92-97MC x=0..5A, S, R
ADCTRIGx98-108ADC TRIG x=0..10A, S, R
ACSOCx109-110AC SOC x=0..1A, S, R
PTC DSEQR111 -A
STCONV112 -A
HSMTAMPERx113-116x = 1..4A
Note:
  1. A = Asynchronous path, S = Synchronous path, R = Resynchronized path