18.7.6 External Multipurpose Crystal Oscillator Control A

Table 18-9. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	XOSCCTRLA
Offset:	0x14
Reset:	0x00000D00
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24
	WRTLOCK						USBHSDIV[1:0]
Access	R/W						R/W	R/W
Reset	0						0	0


Bit	23	22	21	20	19	18	17	16
					CFDPRESC[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	15	14	13	12	11	10	9	8
					STARTUP[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ONDEMAND		SWBEN	CFDEN	XTALEN	AGC	ENABLE
Access	R/W		R/W	R/W	R/W	R/W	R/W
Reset	0		0	0	0	0	0

Bit 31 – WRTLOCK Write Lock for CTRLA register

Note: Once the WRTLOCK bit is set, it can only be cleared by a reset.

Value	Description
0	The XOSCCTRLA register can be modified by a system write.
1	The XOSCCTRLA (except XOSCCTRLA.SWBEN) register is write protected.

Bits 25:24 – USBHSDIV[1:0] USBHS Reference Clock Division

These bits select the XOSC division factor for the USBHS PLL reference clock. These bits are XOSCCTRLA.ENABLE protected and cannot be updated if XOSCCTRLA.ENABLE=1.


Value	Name	Description
0x0	DIS	USBHSPLL reference XOSC clock is disabled
0x1	DIV1	USBHSPLL reference XOSC clock is divided by 1
0x2	DIV2	USBHSPLL reference XOSC clock is divided by 2
0x3	DIV4	USBHSPLL reference XOSC clock is divided by 4

Bits 19:16 – CFDPRESC[3:0] Clock Failure Detector Prescaler

These bits select the DFLL48oscillator post scaler for the clock fail detector. The CFD safe clock frequency is the DFLL48 frequency divided by 2^CFDPRESC. These bits are XOSCCTRLA.ENABLE protected and cannot be updated if XOSCCTRLA.ENABLE=1

Bits 11:8 – STARTUP[3:0] Start-Up Time for External Multipurpose Crystal Oscillator

These bits select start-up time for the oscillator XOSC according to the table below before a clock fail is acknowledged. The OSCULP32K oscillator is used to clock the start-up counter. These bits are XOSCCTRLA.ENABLE protected and cannot be updated if XOSCCTRLA.ENABLE = 1.


STARTUP[3:0]	Number of OSCULP32KClock Cycles	Approximate Equivalent Time
0x0	1	31µs
0x1	2	61μs
0x2	4	122μs
0x3	8	244μs
0x4	16	488μs
0x5	32	977μs
0x6	64	1953μs
0x7	128	3906μs
0x8	256	7813μs
0x9	512	15625μs
0xA	1024	31250μs
0xB	2048	62500μs
0xC	4096	125000μs
0xD (Default)	8192	250000μs
0xE	16384	500000μs
0xF	32768	1000000μs

Note:

It is critical when using AGC to allow ample startup time to avoid spurious CFD events.
When using AGC BW = 0x0, the minimum startup time is 6.25 ms.

Bit 7 – ONDEMAND On Demand Control

The ONDEMAND operation mode allows the XOSC to be enabled or disabled depending on peripheral clock requests.

Note: The XOSC is not running if no peripheral is requesting the clock source.

If ONDEMAND is set, the XOSC will only be running when requested by a peripheral and enabled (XOSCTRLA.ENABLE = 1). If there is no peripheral requesting the XOSC’s clock source, the XOSC will be in a disabled state. If ONDEMAND is disabled, the XOSC will always be running when enabled (XOSCTRLA.ENABLE = 1). In Standby Sleep mode, the ONDEMAND operation is still active. This bit is XOSCCTRLA.ENABLE protected and cannot be updated if XOSCCTRLA.ENABLE = 1.

Value	Description
0	The XOSC is always on.
1	The XOSC is running when a peripheral is requesting the XOSC to be used as a clock source.

Bit 5 – SWBEN XOSC Clock Switch Back Enable

This bit controls the XOSC output clock switch back to the external clock or crystal oscillator in case of clock recovery.

Note: The SWBEN bit is also cleared when the Clock Failure Detector is disabled (CFDEN = 0).

Value	Description
0	The clock switch back is disabled.
1	The clock switch back is enabled. This bit is reset once the XOSC output clock is switched back to the external clock or crystal oscillator.

Bit 4 – CFDEN Clock Failure Detector Enable

This bit controls the XOSC clock failure detector and is enable protected

Note: After setting CFDEN to enable clock failure detection, STATUS.CLKFAIL will always be set. This first detection must be ignored. Subsequent setting of this bit will indicate actual clock failure events.

Value	Description
0	Clock Failure Detector is disabled.
1	Clock Failure Detector is enabled.

Bit 3 – XTALEN Crystal Oscillator Enable

This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC.

Note:

If XOSCCTRLA.XTALEN = 0 then XOSCCTRLA.AGC = 1 is not permitted.
This bit is XOSCCTRLA.ENABLE protected and cannot be updated if XOSCCTRLA.ENABLE = 1.
If XOSCCTRLA.XTALEN = 0 then XOSCCTRLB.GMAN (User Manual Gain control) bits are ignored.

Value	Description
0	External clock oscillator connected on XIN. XOUT can be used as general-purpose I/O.
1	Crystal connected to XIN and XOUT.

Bit 2 – AGC Auto Gain Control Loop Enable

Note:

If XOSCCTRLA.XTALEN = 0 then XOSCCTRLA.AGC = 1 is not permitted.
This bit is XOSCCTRLA.ENABLE protected and cannot be updated if XOSCCTRLA.ENABLE = 1.
If AGC is enabled, XOSCCTRLB.GMAN (User Manual Gain control) bits are ignored.
When the XOSCCTRLA.AGC = 1, the Primary Oscillator will automatically do a linear search to find the lowest power/gain setting to guarantee stable oscillation with the user’s crystal.