42.2 Features

Up to 12-bit resolution of the numerical output, signed or unsigned (higher resolutions possible with oversampling).

  • Signed/Unsigned results
  • Left or Right aligned result
  • Fractional or integer results
  • Up to 4.6875 Msps conversion rate in 12-bit resolution mode
  • Throughput rates (See the Electrical Specifications):
    Note: Assumes GCLK_ADC = 150 MHz, TAD = 1/75 MHz = 13.33333 ns.
    • Non-Interleaved ADC 1, 2, 3 modules:
      • 12-bit resolution: 4.687500 Msps
      • 10-bit resolution: 5.357142 Msps
    • ADC 0 module:
      • 12-bit resolution: 3.947368 Msps
      • 10-bit resolution: 4.411764 Msps
    • Interleaved ADC 1, 2, 3 modules only:
      • 12-bit resolution: 13.636363 Msps
      • 10-bit resolution: 15 Msps
    • Interleaved ADC 0, 1, 2, 3 modules:
      • 12-bit resolution: 15 Msps
      • 10-bit resolution: 16.666666 Msps
  • Maximum of 16 unique external analog input channels.
    • AIN[15:0] ADC Module 0
    • AIN[5:0] ADC1, ADC2, and ADC3 Modules
  • Internal inputs:
    • VDDCORE internal analog channel AIN6 on ADC1 module
    • Temperature Sensor internal analog channel AIN6 on ADC2 module
    • IVREF 1.2v, internal analog channel AIN6 on ADC3 module
  • ADC0 16 single ended external analog inputs, (i.e., no differential channels on ADC0 Module).
  • ADC1/2/3 six single ended external analog inputs or up to three differential inputs plus one internal channel
  • Up to 16 trigger sources, off-chip hardware or on-chip hardware or software generated per analog input channel
  • Edge or level active triggering modes, generating single conversions or bursts of conversions
  • A scan trigger per each shared Analog ADC module to start a scan cycle which can individually include or not include any of the analog inputs assigned to that ADC module assuming that the different ADC modules are assigned the same scan trigger source
  • Supports up to four scan cycles running simultaneously on different ADC modules
  • Any of the 16 trigger sources or the scan triggers can be assigned to individual analog input channels
  • The scan trigger itself can select any of the 16 trigger sources as its own source
  • Programmable sampling time, individually set for each ADC, CORCTRLx.SAMC.
  • Each analog input/channel output register can be read from a general dedicated output register (write to the CORDYID and CHRDYID registers and then reads the CHRDYDATA register)
  • 16 sample deep FIFO supporting all channels
  • Four Digital Comparators for monitoring output values in relation to user-specified ADC result thresholds.
    Note: There can be at most one digital comparator assigned to each ADC module, because only one channel per Analog ADC module can be converted at a time.
  • Four digital filters; providing averaging/oversampling for increased noise immunity and are assignable to any analog input.
    Note: There can be at most one digital filter assigned to each ADC module, because only one channel per ADC module can be converted at a time.