32.8.125 Receive DMA Data Buffer Address Mask
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | DMAAM |
| Offset: | 0x00D0 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| MVAL[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MEN[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 31:28 – MVAL[3:0] Receive DMA Data Buffer Mask Value
Values used to force bits 31:28 of the receive data buffer AHB/AXI address to a particular value when the associated enable bits stored in this register [3:0] are set. Any changes to this register will be ignored while the DMA is currently processing a receive packet. It will only affect the next full packet to be written to external system memory.
Bits 3:0 – MEN[3:0] Receive DMA Data Buffer Mask Enable
These bits are associated directly with bits [31:28].
When bit 0 is set, the AHB/AXI address bit 28 used for accessing the receive data buffers will be forced to the value stored in bit 28 of this register.
When bit 1 is set, the AHB/AXI address bit 29 used for accessing the receive data buffers will be forced to the value stored in bit 29 of this register.
When bit 2 is set, the AHB/AXI address bit 30 used for accessing the receive data buffers will be forced to the value stored in bit 30 of this register.
When bit 3 is set, the AHB/AXI address bit 31 used for accessing the receive data buffers will be forced to the value stored in bit 31 of this register.
When these bits are clear, the associated value stored in bits 31:28 have no effect on the AHB/AXI address used for receive data buffer accesses. Any changes to this register will be ignored while the DMA is currently processing a receive packet. It will only affect the next full packet to be written to external memory.