28.8.4 CLCnSEL0

Generic CLCn Data 1 Select Register
Name: CLCnSEL0
Offset: 0x068E

Bit 76543210 
  D1S[6:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset xxxxxxx 

Bits 6:0 – D1S[6:0] CLCn Data1 Input Selection

Table 28-2. CLC Input Selection
DyS Input SourceDyS (cont.)Input Source (cont.)
[0] 0000 0000CLCIN0PPS[19] 0001 0011—
[1] 0000 0001CLCIN1PPS[20] 0001 0100CCP1_OUT
[2] 0000 0010CLCIN2PPS[21] 0001 0101CCP2_OUT
[3] 0000 0011CLCIN3PPS[22] 0001 0110-[30] 0001 1110—
[4] 0000 0100FOSC[31] 0001 1111C1_OUT
[5] 0000 0101HFINTOSC [32] 0010 0000C2_OUT
[6] 0000 0110LFINTOSC [33] 0010 0001—
[7] 0000 0111MFINTOSC (500 kHz) [34] 0010 0010IOCIF
[8] 0000 1000MFINTOSC (32 kHz) [35] 0010 0011CLC1_OUT
[9] 0000 1001SFINTOSC (1 MHz)[36] 0010 0100CLC2_OUT
[10] 0000 1010—[37] 0010 0101CLC3_OUT
[11] 0000 1011EXTOSC[38] 0010 0110CLC4_OUT
[12] 0000 1100ADCRC[39] 0010 0111TX1/CK1
[13] 0000 1101—[40] 0010 1000—
[14] 0000 1110TMR0_Overflow[41] 0010 1001SDA1/SDO1
[15] 0000 1111TMR1_Overflow[42] 0010 1010SCL1/SCK1
[16] 0001 0000TMR2_Postscaled_OUT[43] 0010 1011-[46] 0010 1110—
[17] 0001 0001—[47] 0010 1111PWM1_OUT
[18] 0001 0010—[48] 0011 0000PWM2_OUT
[49] 0011 0001-[127] 0111 1111—
Reset States: 
POR/BOR = xxxxxxx
All Other Resets = uuuuuuu