23.10.5 TxCLKCON

Timer Clock Source Selection Register

Name:	TxCLKCON
Offset:	0x0390


Bit	7	6	5	4	3	2	1	0
				CS[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 4:0 – CS[4:0] Timer Clock Source Selection

Table 23-3. Clock Source Selection
CS	Clock Source
`11111-10100`	Reserved
`10011`	CLB_BLE[10]
`10010`	CLB_BLE[9]
`10001`	CLB_BLE[8]
`10000`	CLB_BLE[7]
`01111`	CLC4_OUT
`01110`	CLC3_OUT
`01101`	CLC2_OUT
`01100`	CLC1_OUT
`01011-01001`	Reserved
`01000`	EXTOSC
`00111`	Reserved
`00110`	MFINTOSC (32 kHz)
`00101`	MFINTOSC (500 kHz)
`00100`	LFINTOSC
`00011`	HFINTOSC
`00010`	F_OSC
`00001`	F_OSC/4
`00000`	Pin selected by T2INPPS

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.