2 Pin Diagrams

Figure 2-1. 8-Pin PDIP, SOIC, DFN

Figure 2-2. 14-Pin SOIC, TSSOP

Figure 2-3. 20-Pin PDIP, SOIC, SSOP

Figure 2-4. 20-Pin VQFN

Note: It is recommended that the exposed bottom pad be connected to V_SS; however, it must not be the only V_SS connection to the device.