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PIC16F13145 Family Full-Featured 8/14/20-Pin Microcontrollers
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PIC16F13113
PIC16F13114
PIC16F13115
PIC16F13123
PIC16F13124
PIC16F13125
PIC16F13143
PIC16F13144
PIC16F13145
Introduction
PIC16F13145
Family Summary
Core Features
Memory
Operating Characteristics
Power-Saving Functionality
Digital Peripherals
Analog Peripherals
Clocking Structure
Programming/Debug Features
1
Packages
2
Pin Diagrams
3
Pin Allocation Tables
4
Guidelines for Getting Started with
PIC16F13145
Microcontrollers
4.1
Basic Connection Requirements
4.2
Power Supply Pins
4.3
Master Clear (
MCLR
) Pin
4.4
In-Circuit Serial Programming™ (ICSP™) Pins
4.5
Unused I/Os
5
Register and Bit Naming Conventions
5.1
Register Names
5.2
Bit Names
5.3
Register and Bit Naming Exceptions
6
Register Legend
7
Enhanced Mid-Range CPU
7.1
Automatic Interrupt Context Saving
7.2
16
-Level Stack with Overflow and Underflow
7.3
File Select Registers
7.4
Instruction Set
8
Device Configuration
8.1
Configuration Words
8.2
Code Protection
8.3
Write Protection
8.4
User ID
8.5
Device ID and Revision ID
8.6
Register Definitions: Configuration Settings
8.7
Register Definitions: Device ID and Revision ID
9
Memory Organization
9.1
Program Memory Organization
9.2
Data Memory Organization
9.3
STATUS Register
9.4
PCL and PCLATH
9.5
Stack
9.6
Indirect Addressing
9.7
Register Definitions: Memory Organization
9.8
Register Summary - Memory Organization
10
Resets
10.1
Power-on Reset (POR)
10.2
Brown-out Reset (BOR)
10.3
MCLR
Reset
10.4
Windowed Watchdog Timer (WWDT) Reset
10.5
Watchdog Timer (WDT) Reset
10.6
RESET
Instruction
10.7
Stack Overflow/Underflow Reset
10.8
Power-Up Timer (PWRT)
10.9
Start-Up Sequence
10.10
Memory Execution Violation
10.11
Determining the Cause of a Reset
10.12
Power Control (PCONx) Register
10.13
Register Definitions: Power Control
10.14
Register Summary - Power Control
11
OSC - Oscillator Module (With Fail-Safe Clock Monitor)
11.1
Clock Source Types
11.2
Clock Switching
11.3
Fail-Safe Clock Monitor (FSCM)
11.4
Register Definitions: Oscillator Module
11.5
Register Summary - Oscillator Module
12
INT - Interrupts
12.1
Overview
12.2
INTCON Register
12.3
PIE Registers
12.4
PIR Registers
12.5
Operation
12.6
Interrupt Latency
12.7
Interrupts During Sleep
12.8
INT Pin
12.9
Automatic Context Saving
12.10
Register Definitions: Interrupt Control
12.11
Register Summary - Interrupt Control
13
Power-Saving Modes
13.1
Doze Mode
13.2
Sleep Mode
13.3
Idle Mode
13.4
Peripheral Operation in Power-Saving Modes
13.5
Register Definitions: Power-Savings Control
13.6
Register Summary - Power-Savings Control
14
WWDT - Windowed Watchdog Timer
14.1
Independent Clock Source
14.2
WWDT Operating Modes
14.3
Time-Out Period
14.4
Watchdog Window
14.5
Clearing the Watchdog Timer
14.6
Operation During Sleep
14.7
Register Definitions: Windowed Watchdog Timer Control
14.8
Register Summary - WDT Control
15
NVM - Nonvolatile Memory Control
15.1
Program Flash Memory (PFM)
15.2
Register Definitions: Nonvolatile Memory Control
15.3
Register Summary - NVM Control
16
I/O Ports
16.1
Overview
16.2
PORTx - Data Register
16.3
LATx - Output Latch
16.4
TRISx - Direction Control
16.5
ANSELx - Analog Control
16.6
WPUx - Weak Pull-Up Control
16.7
INLVLx - Input Threshold Control
16.8
SLRCONx - Slew Rate Control
16.9
ODCONx - Open-Drain Control
16.10
Edge Selectable Interrupt-on-Change
16.11
I
2
C Pad Control
16.12
I/O Priorities
16.13
MCLR
/V
PP
/RA3
Pin
16.14
Register Definitions: Port Control
16.15
Register Summary - I/O Ports
17
IOC - Interrupt-on-Change
17.1
Overview
17.2
Enabling the Module
17.3
Individual Pin Configuration
17.4
Interrupt Flags
17.5
Clearing Interrupt Flags
17.6
Operation in Sleep
17.7
Register Definitions: Interrupt-on-Change Control
17.8
Register Summary - Interrupt-on-Change
18
PPS - Peripheral Pin Select Module
18.1
Overview
18.2
PPS Inputs
18.3
PPS Outputs
18.4
Bidirectional Pins
18.5
PPS Lock
18.6
Operation During Sleep
18.7
Effects of a Reset
18.8
Register Definitions: Peripheral Pin Select (PPS)
18.9
Register Summary - Peripheral Pin Select Module
19
CRC - Cyclic Redundancy Check Module with Memory Scanner
19.1
Module Overview
19.2
Polynomial Implementation
19.3
Data Sources
19.4
CRC Check Value
19.5
CRC Interrupt
19.6
Configuring the CRC Module
19.7
Scanner Module Overview
19.8
Scanning Modes
19.9
Configuring the Scanner
19.10
Scanner Interrupts
19.11
WWDT Interaction
19.12
Operation During Sleep
19.13
Peripheral Module Disable
19.14
Register Definitions: CRC and Scanner Control
19.15
Register Summary - CRC
20
PMD - Peripheral Module Disable
20.1
Overview
20.2
Disabling a Module
20.3
Enabling a Module
20.4
Register Definitions: Peripheral Module Disable
20.5
Register Summary - PMD
21
TMR0 - Timer0 Module
21.1
Timer0 Operation
21.2
Clock Selection
21.3
Timer0 Output and Interrupt
21.4
Operation During Sleep
21.5
Register Definitions: Timer0 Control
21.6
Register Summary - Timer0
22
TMR1 - Timer1 Module with Gate Control
22.1
Timer1 Operation
22.2
Clock Source Selection
22.3
Timer1 Prescaler
22.4
Timer1 Operation in Asynchronous Counter Mode
22.5
Timer1 16-Bit Read/Write Mode
22.6
Timer1 Gate
22.7
Timer1 Interrupt
22.8
Timer1 Operation During Sleep
22.9
CCP Capture/Compare Time Base
22.10
CCP Special Event Trigger
22.11
Peripheral Module Disable
22.12
Register Definitions: Timer1 Control
22.13
Register Summary - Timer1
23
TMR2 - Timer2 Module
23.1
Timer2 Operation
23.2
Timer2 Output
23.3
External Reset Sources
23.4
Timer2 Interrupt
23.5
PSYNC Bit
23.6
CSYNC Bit
23.7
Operating Modes
23.8
Operation Examples
23.9
Timer2 Operation During Sleep
23.10
Register Definitions: Timer2 Control
23.11
Register Summary - Timer2
24
CCP - Capture/Compare/PWM Module
24.1
CCP Module Configuration
24.2
Capture Mode
24.3
Compare Mode
24.4
PWM Overview
24.5
Register Definitions: CCP Control
24.6
Register Summary - CCP Control
25
Capture, Compare, and PWM Timers Selection
25.1
Register Definitions: Capture, Compare, and PWM Timers Selection
25.2
Register Summary - Capture, Compare, and PWM Timers Selection
26
PWM - Pulse-Width Modulation
26.1
Fundamental Operation
26.2
PWM Output Polarity
26.3
PWM Period
26.4
PWM Duty Cycle
26.5
PWM Resolution
26.6
Operation in Sleep Mode
26.7
Changes in System Clock Frequency
26.8
Effects of Reset
26.9
Setup for PWM Operation Using PWMx Output Pins
26.10
Setup for PWM Operation to Other Device Peripherals
26.11
Register Definitions: PWM Control
26.12
Register Summary - PWM
27
PWM Timers Selection
27.1
Register Definitions: Capture, Compare, and PWM Timers Selection
27.2
Register Summary - Capture, Compare, and PWM Timers Selection
28
CLC - Configurable Logic Cell
28.1
CLC Setup
28.2
CLC Interrupts
28.3
Effects of a Reset
28.4
Output Mirror Copies
28.5
Operation During Sleep
28.6
CLC Setup Steps
28.7
Register Overlay
28.8
Register Definitions: Configurable Logic Cell
28.9
Register Summary - CLC Control
29
CLB - Configurable Logic Block
29.1
CLB Module Enable
29.2
Basic Logic Element (BLE)
29.3
Dedicated 3-Bit Counter
29.4
CLB Module Inputs
29.5
CLB Outputs
29.6
CLB Clock Selection
29.7
CLB Interrupts
29.8
CLB Configuration
29.9
Register Definitions: Configurable Logic Block
29.10
Register Summary - CLB Control
30
MSSP - Host Synchronous Serial Port Module
30.1
SPI Mode Overview
30.2
I
2
C Mode Overview
30.3
Baud Rate Generator
30.4
Register Definitions: MSSP Control
30.5
Register Summary - MSSP Control
31
EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter
31.1
EUSART Asynchronous Mode
31.2
Clock Accuracy with Asynchronous Operation
31.3
EUSART Baud Rate Generator (BRG)
31.4
EUSART Synchronous Mode
31.5
EUSART Operation During Sleep
31.6
Register Definitions: EUSART Control
31.7
Register Summary - EUSART
32
ADC - Analog-to-Digital Converter with Computation Module
32.1
ADC Configuration
32.2
ADC Operation
32.3
ADC Acquisition Requirements
32.4
Computation Operation
32.5
Register Definitions: ADC Control
32.6
Register Summary - ADC
33
DAC - Digital-to-Analog Converter Module
33.1
Output Voltage Selection
33.2
Ratiometric Output Level
33.3
Buffered DAC Output Range Selection
33.4
Operation During Sleep
33.5
Effects of a Reset
33.6
Register Definitions: DAC Control
33.7
Register Summary - DAC
34
CMP - Comparator Module
34.1
Comparator Overview
34.2
Comparator Control
34.3
Comparator Hysteresis
34.4
Comparator Interrupt
34.5
Comparator Positive Input Selection
34.6
Comparator Negative Input Selection
34.7
Comparator Response Time
34.8
Analog Input Connection Considerations
34.9
Operation in Sleep Mode
34.10
ADC Auto-Trigger Source
34.11
Register Definitions: Comparator Control
34.12
Register Summary - Comparator
35
FVR - Fixed Voltage Reference
35.1
Independent Gain Amplifiers
35.2
FVR Stabilization Period
35.3
Register Definitions: FVR
35.4
Register Summary - FVR
36
Temperature Indicator Module
36.1
Module Operation
36.2
Temperature Calculation
36.3
ADC Acquisition Time
36.4
Register Definitions: Temperature Indicator
36.5
Register Summary - Temperature Indicator
37
Charge Pump
37.1
Manually Enabled
37.2
Automatically Enabled
37.3
Disabled
37.4
Charge Pump Oscillator
37.5
Charge Pump Threshold
37.6
Charge Pump Ready
37.7
Register Definitions: Charge Pump
37.8
Register Summary - Charge Pump
38
Instruction Set Summary
38.1
Read-Modify-Write Operations
38.2
Standard Instruction Set
39
ICSP™ - In-Circuit Serial Programming™
39.1
High-Voltage Programming Entry Mode
39.2
Low-Voltage Programming Entry Mode
39.3
Common Programming Interfaces
40
Register Summary
41
Electrical Specifications
41.1
Absolute Maximum Ratings
(†)
41.2
Standard Operating Conditions
41.3
DC Characteristics
41.4
AC Characteristics
42
DC and AC Characteristics Graphs and Tables
43
Packaging Information
43.1
Package Details
44
Appendix A: Revision History
Microchip Information
The Microchip Website
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