12.10.3 PIE1
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt controlled by registers PIE1 through PIE4.
| Name: | PIE1 |
| Offset: | 0x0097 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TMR2IE | TMR3GIE | TMR3IE | TMR1GIE | TMR1IE | ACTIE | NVMIE | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – TMR2IE TMR2 Interrupt Enable
| Value | Description |
|---|---|
| 1 | TMR2 interrupts are enabled |
| 0 | TMR2 interrupts are disabled |
Bit 6 – TMR3GIE TMR3 Gate Interrupt Enable
| Value | Description |
|---|---|
| 1 | TMR3 Gate interrupts are enabled |
| 0 | TMR3 Gate interrupts are disabled |
Bit 5 – TMR3IE TMR3 Interrupt Enable
| Value | Description |
|---|---|
| 1 | TMR3 interrupts are enabled |
| 0 | TMR3 interrupts are disabled |
Bit 4 – TMR1GIE TMR1 Gate Interrupt Enable
| Value | Description |
|---|---|
| 1 | TMR1 Gate interrupts are enabled |
| 0 | TMR1 Gate interrupts are disabled |
Bit 3 – TMR1IE TMR1 Interrupt Enable
| Value | Description |
|---|---|
| 1 | TMR1 interrupts are enabled |
| 0 | TMR1 interrupts are disabled |
Bit 2 – ACTIE Active Clock Tuning Interrupt Enable
| Value | Description |
|---|---|
| 1 | Active Clock Tuning interrupts are enabled |
| 0 | Active Clock Tuning interrupts are disabled |
Bit 0 – NVMIE NVM Interrupt Enable
| Value | Description |
|---|---|
| 1 | NVM interrupts are enabled |
| 0 | NVM interrupts are disabled |