3.1 Overview

Smart high-level synthesis (SmartHLS™) Compiler is an Eclipse-based integrated development environment that takes C++ software code as input and generates a SmartDesign IP component (Verilog HDL) as an output. Hardware engineers can instantiate the generated SmartDesign IP component in the SmartDesign Canvas available in Libero® SoC design suite to build an FPGA system.

SmartHLS automatically compiles a C/C++ program into hardware described in Verilog HDL (Hardware Description Language). The generated hardware can be programmed onto an Microchip® FPGA (Field-Programmable Gate Array). Hardware implemented on an FPGA can provide 2-10X performance and power benefits over the same computation running on regular processors.

SmartHLS includes C/C++ to Verilog high-level synthesis tool and is tested on Windows and Linux 64-bit Operating systems.

The following table describes each document shipped withSmartHLS.