13.2 Design Flows with SmartTime
(Ask a Question)You can access SmartTime in Libero SoC during the following design implementation phases:
- During Place and Route—when you select timing-driven place-and-route, SmartTime runs in the background to provide accurate timing information.
- After Place and Route—run SmartTime to perform
post-layout timing analysis and adjust timing constraints. In the
Libero SoC Design Flow window, expand Implement Design
> Verify Post-Layout Implementation and then either:
- Double-click Verify Timing to generate Timing Reports.
- Right-click Open SmartTime > Open Interactively to run SmartTime.
- During Back-Annotation—SmartTime runs in the background to generate the SDF file for timing simulation.
You can also run SmartTime to generate Timing Reports, regardless of which design implementation phase you are in.
For more information about Place and Route and Back-Annotation, see the Libero SoC Design Flow User Guide .