5.1 Overview

The following topics provide an overview of Libero SoC.

5.1.1 Libero SoC Design Flow

The following figure shows the Libero SoC design flow.

Figure 5-1. Libero SoC Design Flow
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5.1.1.1 Creating the Design

Create your design with the following design capture tools:

  • System Builder
  • Create SmartDesign
  • Create HDL
  • Create SmartDesign Testbench (optional, for simulation only)
  • Create HDL Testbench (optional, for simulation only)

After you create the design, start the simulation for pre-synthesis verification.

You can also click the

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button to start the Libero SoC software through Place and Route with default settings. However, doing so bypasses constraint management.

5.1.1.2 Working with Constraints

In the FPGA design world, constraint files are as important as design source files. Constraint files are used throughout the FPGA design process to guide FPGA tools to achieve the timing and power requirements of the design. For the synthesis step, SDC timing constraints set the performance goals whereas non-timing FDC constraints guide the Synthesis tool for optimization. For the Place and Route step, SDC timing constraints guide the tool to achieve the timing requirements, whereas Physical Design Constraints (PDC) guide the tool for optimized placement and routing (Floorplanning). For Static Timing Analysis, SDC timing constraints set the timing requirements and design-specific timing exceptions for static timing analysis.

Libero SoC provides the Constraint Manager to manage your design constraint needs. Constraint Manager is a single centralized graphical interface that allows you to create, import, link, check, delete, and edit design constraints, and associate the constraint files to design tools in the Libero SoC environment. Constraint Manager also allows you to manage constraints for SynplifyPro synthesis, Libero SoC Place and Route, and the SmartTime Timing Analysis throughout the design process.

After project creation, double-click Manage Constraints in the Design Flow window to open the Constraint Manager.

Figure 5-2. Constraint Manager

5.1.1.2.1 Constraint Flow and Design Sources

The Constraint flow supports HDL and Netlist design sources. The Libero SoC Design Flow window and the Constraint Manager are context-sensitive according to whether the design source is HDL or Netlist.

5.1.1.2.2 Constraint Flow for VM Netlist Designs

When the design source is a Netlist, the Design Flow window displays Compile Netlist as a design step. Timing constraints can be passed to Place and Route and Timing Verification only.

The options to promote or demote global resources of the chip are set in the Compile Netlist options. The following figure compares and contrasts the HDL flow versus the Netlist flow.

Table 5-2. HDL Flow vs. Netlist Flow

HDL Flow

Netlist Flow

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Design Flow Window

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Design Flow Window

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Constraint Manager

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Constraint Manager

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Constraint Manager - Check *.fdc and *.ndc

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Constraint Manager - Check *.ndc only

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Global Promotion/Demotion Options set in Synthesis Options Dialog Box

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Global Promotion/Demotion Options set in Compile Netlist Options Dialog Box

5.1.1.2.3 Constraint Flow for HDL Designs

When the design source is HDL, the Design Flow window displays Synthesis as a design step. The Constraint Manager also makes available Synthesis as a target to receive timing constraints and netlist attribute constraints. The options to promote or demote global resources of the chip are set in the Synthesis options.

5.1.1.3 Implementing the Design

The following references provide information about implementing your design.

5.1.1.4 Programming and Debugging the Design

The following topics provide information about programming and debugging your design.

Generating and Updating Data

Configuring the Hardware

Programming the Design

Debugging the Design

5.1.2 File Types in Libero SoC

Creating a new project in Libero SoC creates new directories and project files automatically. The project directory contains your local project files. When you import files from outside your current project, the files are copied into your local project folder.

The Project Manager allows you to manage your files as you import them. For example, to store and maintain your design source files and design constraint files in a central location outside the project location, you can link them to the Libero project folders when you created the project. These files are linked, not copied, to the project folder.

Depending on your project preferences and the installed version of Libero SoC, the software creates directories for your project. The following table describes these directories.
Table 5-3. Libero SoC Directories
<project_name>

This is the top-level directory. It contains the *.prjx file. Only one *.prjx file is enabled for each Libero SoC project. If you associate Libero SoC as the default program with the *.prjx file (Project > Preferences > Startup > Check the default file association (.prjx) at startup), you can open the project with Libero SoC by double-clicking the *.prjx file.

componentContains SmartDesign components (.sdb and .cxf files) and the *_manifest.txt file for each design component in your Libero SoC project. To run synthesis, simulation, and firmware development with your own point tools outside the Libero SoC environment, see the *_manifest.txt file. For each design component, Libero SoC generates a <component_name>_manifest.txt file that stores the file name and location of:
  • HDL source files to be used for synthesis and simulations
  • Stimulus files and configuration files for simulation
  • Firmware files for software IDE tools
  • Configuration files for programming
  • Configuration files for power analysis

To run synthesis, simulation, firmware development, programming, and power analysis outside the Libero SoC environment, see the SmartFusion 2/IGLOO 2 Custom Flow User Guide.

Note: When importing components, make sure that .sdb and .cxf files reside in the same directory.
constraintContains all the constraint files:
  • SDC timing constraint files
  • Floorplanning PDC files
  • I/O PDC files
  • Netlist Attributes NDC files
designerContains the following files:
  • For Silicon Explorer: *_ba.sdf, *_ba.v(hd), STP, and PRB
  • To run designer: TCL
  • Local project file relative to revision: impl.prj_des
  • Log file: designer.log
hdlContains all HDL sources:
  • VHDL: *.vhd files
  • Verilog: *.v and *.h files
simulationContains the following files for simulation:
  • meminit.dat
  • modelsim.ini
  • *.bfm
  • *.vec file
  • run.do
smartgenContains GEN files and LOG files from generated cores.
stimulusContains BTIM, Verilog, and VHDL stimulus files.
synthesisContains files generated by the tools (not managed by Libero SoC), including:
  • *.vm file
  • Synplify log file: *_syn.prj
  • Precision project file: *.psp
  • Synplify log file: *.srr
  • Precision log file: precision.log
  • To run synthesis: *.tcl
viewdrawContains viewdraw.ini files.

5.1.2.1 Internal Files

Libero SoC generates the following internal files, some of which are encrypted. These files are for Libero SoC housekeeping and are not intended for you to use.

FileFile ExtensionRemarks

Routing Segmentation File

*.segNone

Combiner Info

*.cobNone

Hierarchical Netlist

*.adlNone

Flattened Netlist

*.aflNone

Location file

*.locNone

map file

*.map

Fabric Programming File

tieoffs.txt

*.txt

RTG4 devices only

5.1.3 Software Tools

Libero SoC integrates design tools, streamlines design flow, manages design and log files, and passes design data between tools. The following table identifies the tools you can use to perform Libero SoC functions. For more information about Libero SoC tools, visit www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/fpga/libero-software-later-versions#overview.

Table 5-4. Matching Functions with Tools
FunctionToolComments

Project Manager, HDL Editor, Core Generation

Libero SoC

Project Manager, HDL Editor targets the creation of HDL code. HDL Editor supports VHDL and Verilog with color, highlighting keywords for both HDL languages.

Synthesis

Synplify® Pro ME

Synplify Pro ME is integrated as part of the design package, enabling designers to target HDL code to specific devices.

Simulation

ModelSim® ME ProAllows source-level verification so designers can verify HDL code. Designers can perform simulation at all levels: behavioral (or pre-synthesis), structural (or post-synthesis), and dynamic simulation.

Timing/Constraints, Power Analysis, Netlist Viewer, Floorplanning, Package Editing, Place and Route, Debugging

Libero SoC

This software package includes:
  • ChipPlanner: displays I/O and logic macros in your design for floorplanning
  • Netlist Viewer: design schematic viewer.
  • SmartPower: power analysis tool.
  • SmartTime: static timing analysis and constraints editor.

5.1.4 Software IDE Integration

Libero SoC simplifies the task of transitioning between designing your FPGA and developing your embedded firmware by managing the firmware for your FPGA hardware design. This includes managing:

  • Firmware hardware abstraction layers required for your processor.
  • Firmware drivers for the processor peripherals in your FPGA design.
  • Sample application projects available for drivers that show how to use the APIs properly.

To see which firmware drivers Libero SoC found to be compatible with your design, open the Firmware View. From this view, you can change the configuration of your firmware, change to a different version, read driver documentation, and generate sample projects for each driver.

Libero SoC manages the integration of your firmware with your preferred Software Development Environment, including SoftConsole, Keil, and IAR Embedded Workbench. The projects and workspace for your selected development environment are generated automatically with the proper settings and flags so you can write your applications immediately.